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Electromigration induced d e gradation in integrated circuits has been accelerated b y c ontinuous scaling of device dimensions. We present a methodology for synthesizing high-reliability and low-energy microarchitectures at the RT level by judiciously binding and scheduling the data transfers of a control data ow graph(CDFG) representation of the application onto the buses in the microarchitecture. The proposed method a c c ounts for correlations between data transfers and the constraints on the number of buses, area and delay.