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We have developed low temperature, low defect, and low cost SiGe selective epitaxial growth (L 3 SiGe SEG) process using a high throughput batch type CVD process at first time. Defect is eliminated by low temperature pre-cleaning and recess shape control. As a result, we have achieved the high quality SiGe SEG, improving the compressive channel stress and reducing the junction leakage. We also improved the NMOS short channel effects by low temperature SiGe SEG. Finally, in combination of low temperature SiGe SEG, dual stress SiN liner, and low thermal budget metallization, drive current of 725 �A/�m in PMOS and 940 �A/�m in NMOS were achieved at off current (I off ) = 100 nA/�m at drain bias (V DD ) = 1.0 V. Introduction Selective epitaxial growth (SEG) of SiGe in a recessed source/drain (S/D) has been considered to be a promising stressor for enhancing the drive current [1]. Epitaxial SiGe S/D gives a compressive channel stress and increases the hole mobility due to the lattice mismatch between SiGe and Si substrate. We have already reported that the defects in SiGe degrade the short channel effects and the hole mobility due to the enhanced B diffusion and the strain relaxation, respectively [2]. Since SiGe/Si hetero structures are metastable with respect to equilibrium, strain tends to relax at higher SiGe growth temperature ( Fig.1) [3]. Moreover, thermal budget of SiGe epitaxial growth has an impact on the short channel effects of NMOS because of dopants re-distribution ( Fig.1). On the other hand, quality of epitaxial SiGe is generally poor at lower growth temperature, generating defects such as pits near side wall spacer as shown in Fig. 2. These pits formations are mainly due to the plasma damage during recess etching and the insufficient removal of interfacial impurities such as O and C. Poor productivity is also one of limits of low temperature process. In this paper, we propose the low temperature, high quality, and high throughput SiGe SEG process and report impacts of SiGe growth temperature on device performance. Device Process Concept A. Newly Proposed Low Temperature EPIConventional SiGe SEG is normally done by single wafer type low-pressure chemical vapor deposition (LPCVD) system at 650-750 o C with dichlorosilane (DCS) � germane (GeH 4 ) -H 2 mixture gases as a SiGe source. As a Si source gas, DCS is suitable for selective growth but not for low temperature growth because growth rate is extremely low as shown in Fig.3. By using silane (SiH 4 ) gas and further optimization, growth rate is enhanced 10 times at 550 o C in compare with DCS case. With increasing HCl partial pressure in this optimized gas mixture, selective growth is achieved even at low temperature of 550 o C, but growth rate is decreased as shown in Fig.4. However poor productivity of low temperature process could be overcome by adopting a new batch type CVD process. Fig.5 shows our newly proposed low temperature batch type CVD sequence. That maximum temperature is below 600 o C. For example, at the SEG temperature of 550 o C, throu...

technology. To achieve aggressively-scaled active, poly, conWe present an aggressively-scaled high-performance and tact, and metal pitches and thus to create 2x pattern density, low-power bulk CMOS platform technology aiming at large-scale high-NA 193-nm immersion lithography was used to expose the (multi-core) high-end use with 45-nm ground rule. By utilizing a critical layers. The FEOL process flow in which MST is the booster high-epsilon offset spacer and FET specific multiple-stressors for improving the performance ofboth N-and PFET is shown in with highly enhanced strain, world competitive high performance Fig. 2. Also, note that this technology is based on the Y-shaped NFET and PFET drive currents of 1.22/0.765 mA/tm at 100 nA/ eSiGe [1] and millisecond annealing (MSA) [2] integration scheme. tm off-current, and 0.97/0.63 mA/tm at 10 nA/gm off-current at The key features of this flow are the implementation of a highVdl = 1V, respectively, were obtained with minimizing layout de-epsilon offset spacer (HEOS) as the extension offset [3] and mulpendence. This technology also offers a functional high density tiple poly-gate stressors (PGSs) or the stress memorization tech-SRAM with a much smaller cell, i.e., 0.255 giM2. In addition, full-nique (SMT) [4]. Implementing the HEOS leads to better perforporous low-k (k = 2.25) BEOL integration lowers RC delay and mance of both the N-and the PFET, whereas the implementing reduces total circuit delay by 25% at the long wiring region com-the PGSs improves the NFET. Fig. 3 shows TEM cross-sections pared to that of our previous technology.of full-processed core FETs with 32-nm gate lengths with welloptimized unit processes. The impact of the HEOS technique on Introduction linear characteristics is shown in Fig. 4. By enhancing the fringThe rapid growth of the market for mobile computers and ing field with high-epsilon spacer material, the parasitic resisdigital consumer electronics, as well as large-scale computer sys-tance of source-drain extension (SDE) under the spacer is signifitems has led to continuing demands for enhanced performance, cantly decreased, and this results in 7 and 10% increases in linear while maintaining low power consumption. This presents us with currents ofN-and PFETs, respectively. A concern in implementthe great challenge of developing the next generation of technol-ing HEOS is the increase of fringe capacitance, which directly ogy nodes. The possibilities offered by gate oxynitride thick-degrades AC performance. The overlap capacitance, Cov, with ness scaling rather than implementing high-k dielectrics are al-and without using HEOS technology is shown in Fig. 5. Ofcourse, ready at their physical limit, and most ofthe potential for improv-high permittivity of offset spacer increases Cov, in which fringe ing performance, as well as for reducing power consumption de-capacitance is also included; however, the effect of improving pends on the multiple-stressor technology (MST) in high perfor-the drive current is much larger and consequently, total ci...