Physical and electrical analysis of the stress memorization technique (SMT) using poly-gates and its optimization for beyond 45-nm high-performance applications

Miyashita, T.; Owada, T.; Hatada, A.; Hayami, Y.; Ookoshi, K.; Mori, Toshihiko; Kurata, H.; Futatsugi, T.

doi:10.1109/iedm.2008.4796612

Cited by 12 publications

(15 citation statements)

References 3 publications

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“…After stressor removal, the high longitudinal tensile stress and vertical compressive stress will be memorized in the channel region. This mechanism explains the increased stress resulting from the use of SPFT to improve electron mobility [10]. Moreover, preamorphous poly-Si during the PAL-A and PAL-B processes offers greater compressive strain.…”

Section: Resultsmentioning

confidence: 98%

Temperature Dependence of Electron Mobility on Strained nMOSFETs Fabricated by Strain-Gate Engineering

Chang

Chao

2012

IEEE Electron Device Lett.

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An effective electron mobility improvement that uses strain-proximity-free technique (SPFT) has been demonstrated using strain-gate engineering. The electron mobility of nMOSFETs with SPFT exhibits a 15% increase over that of counterpart techniques. The preamorphous layer (PAL) gate structure on the SPFT showed a further performance boost. The electron mobility exhibits a 52% improvement in nMOSFET using a combination of SPFT and PAL gate structure. Furthermore, the gain in electron mobility in the SPFT in combination with PAL gate structure decreases at high temperatures. Gate dielectric interface states and ionized gate impurities inducing carrier scattering will play important roles when operating devices under hightemperature conditions.

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Section: Resultsmentioning

confidence: 98%

Temperature Dependence of Electron Mobility on Strained nMOSFETs Fabricated by Strain-Gate Engineering

Chang

Chao

2012

IEEE Electron Device Lett.

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“…Strain is memorized during the S/D activation anneal, followed by a wet etching to remove the capping SiN layer before silicide formation. There exist several theories on the physical mechanisms of SMT, although with no consensus to date [22,23]. The most popular theory on the stress memorization is believed to originate from the compressive stress of n-type poly-Si gate in the vertical direction, which is caused by the poly-Si re-crystallization and volume expansion under the capping layer confinement during the high-temperature anneal.…”

Section: Stress Memorization Technique (Smt)mentioning

confidence: 99%

“…This compressive stress of n-type poly-Si gate then induces a tensile strain in nMOS channel along the longitudinal direction, as illustrated in Figure 5. Several factors can affect the benefit of SMT, including poly amorphorization implant, thickness and rigidity of the high-stress capping layer, and change of capping layer stress before and after hightemperature anneal [22,24,25]. Although in most cases degradation to pMOS is avoided through capping layer removal prior to the high-temperature anneal, it has been reported that the density of SiN used for capping layer can be modified to reduce, or even eliminate the pMOS degradation without going through additional steps of capping layer removal [26].…”

Section: Stress Memorization Technique (Smt)mentioning

confidence: 99%

Advanced strain engineering for state-of-the-art nanoscale CMOS technology

Yang

Cai

2011

Sci. China Inf. Sci.

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The introduction and advancement of strain engineering has been one of the most critical features for the state-of-the-art nanoscale CMOS transistors. This paper provides an overview of the major strain engineering techniques that have remarkably re-shaped the advanced CMOS transistor architecture, including embedded SiGe (eSiGe), embedded Si:C (eSi:C), stress memorization technique (SMT), dual stress liners (DSL), and stress proximity technique (SPT). The advent of high-K/metal-gate (HKMG) also brings in additional strain benefit with its metal gate stressor (MGS) and replacement gate (RMG) process. Strain engineering continues to evolve and will remain to be one of the key performance enablers for the future generation of CMOS technologies. CitationYang B, Cai M. Advanced strain engineering for state-of-the-art nanoscale CMOS technology. Sci China Inf Sci, 2011, 54: 946-958,

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“…For poly-Si implantation, the deeper the R p projection range using the same dosage, the more obvious the stress memorization [6], [7]. With a heavier implant source and the amount of dose aid, the poly-gate condition would be more amorphized [8]. More effective recrystallization would thus occur, and volume swelling could be enhanced significantly.…”

Section: Introductionmentioning

confidence: 99%

Benefit of NMOS by Compressive SiN as Stress Memorization Technique and Its Mechanism

Liao

Chiang

Lin

et al. 2010

IEEE Electron Device Lett.

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Abstract-In this letter, we certify that the compressive SiN capping layer has more potential than the tensile layer for fabrication using the stress memorization technique to enhance NMOS mobility. The mechanism that we have proposed implies that the conventional choice of the capping layer should be modulated from the point of view of stress shift rather than using the highest tensile film.Index Terms-Contact etch-stop layer (CESL), poly amorphization implantation (PAI), strain, stress memorization technique (SMT).

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Physical and electrical analysis of the stress memorization technique (SMT) using poly-gates and its optimization for beyond 45-nm high-performance applications

Cited by 12 publications

References 3 publications

Temperature Dependence of Electron Mobility on Strained nMOSFETs Fabricated by Strain-Gate Engineering

Temperature Dependence of Electron Mobility on Strained nMOSFETs Fabricated by Strain-Gate Engineering

Advanced strain engineering for state-of-the-art nanoscale CMOS technology

Benefit of NMOS by Compressive SiN as Stress Memorization Technique and Its Mechanism

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