Benefit of NMOS by Compressive SiN as Stress Memorization Technique and Its Mechanism

Liao, Chien Chang; Chiang, Tsung‐Yu; Lin, Min-Chen; Chao, Tien−Sheng

doi:10.1109/led.2010.2041524

Cited by 10 publications

(1 citation statement)

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“…Stress film technology has been widely used in the fabrication of advanced transistor. When a stress film is covered on a transistor using a single crystal channel material, the atomic spacing in the channel changes due to tensile or compressive stress, thereby changing the carrier mobility [23,24]. However, the poly-Si channel films have many grain boundaries, and the grain boundary can be acted as a point of stress release to relieve stress, which causes many defects to occur and results in the generation of Nit and NGB.…”

Section: Methodsmentioning

confidence: 99%

Impacts of Vertically Stacked Monolithic 3D-IC Process on Characteristics of Underlying Thin-Film Transistor

Cheng-Yu

Huang

Chen

et al. 2020

IEEE J. Electron Devices Soc.

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In this work, the high-performance junctionless-mode (JL) and low-power inversion-mode (IM) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) with nanosheet channels (less than 10-nm in thickness) are vertically integrated in monolithic three-dimensional integrated circuit (3D-IC) structure. Both JL and IM TFTs can exhibit high on/off current ratio over 10 7 to demonstrate their performance. The JL TFT has much higher on-state current ~ 24 times than it of the IM TFT. And the IM-TFT has much lower SS ~ 0.104 V/decade and off-current ~ 0.04 times than them of the JL TFT. However, the fabrication of the top-devices (JL TFTs) would degrade the performance of underlying-devices (IM TFTs), resulting in the threshold voltage shift of the IM TFTs from 0.61 to 2.17 V, SS increase from 0.104 to 0.218 V/decade and on-state current degradation from 16 to 3 A. In order to further understand the reasons, the IM TFT with top-device removal process is also fabricated, which exhibits a partial recovery in performance. The results indicate the presence and fabrication process of the top-device would lead to the defect generation in the underlying-device. The results provide a new consideration for monolithic 3D-IC manufacturing technology. Index Terms-Monolithic 3D-IC; nanosheet channel; low power; thin-film transistor.

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Section: Methodsmentioning

confidence: 99%