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Clock signal is considered as an immense source of power dissipation in synchronous circuits because of large frequency and load. It does not carry any information but consumes high power at the switching activity which is to be avoided. So, by using clock gating we can save power by reducing unnecessary transition activity inside the gated module. Hence modified design of data driven clock gating and look ahead clock gating is designed to obtain the less power in the circuits. These two techniques are compared among them and by the results obtained through cadence virtuoso tool we can conclude that look ahead clock gating consumes low power, low noise response and higher performance.

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