Design of 3-valued R-S & D type of flip-flops is described. A new clock is developed according to which circuit makes transition as well as retains present, past & former past information. The proposed flip-flops are constructed using clocked T-Gates that reduces the number of transistors required to implement single clocked gates. In the verification by simulation, the proposed flip-flops appears to have lesser power consumption and better speed of operation.

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