No abstract

This paper reports a novel MMIC balanced gate is pumped by the LO signal, and the resulting variation sub-harmonic cold FET mixer for MVDS applications using with time of the FET conductance biased at Vds=OV is used 0.15 gm GaAs pHEMT. The mixer, which includes a LO to mix the IF/RF signals, respectively applied and extracted buffer amplifier, was optimized for highly linear up-conversion from the drain. performance in the 40.5-43.5 GHz RF band, 19.5-20.5 GHz LO band and 2.45-3.45 GHz IF band. A dedicated simulation method has been developed to optimize conversion loss and determine optimum matching. To achieve better (2LO-to-RF) isolation a specific balanced architecture for sub-harmonic In order to optimize conversion losses, it is essential to mixing has been elaborated. This leads to simulation results of 13+0.5dB conversion losses associated to high IF input power determinetheopim s rqie at gate and por at 1dB compression of 17dBm, and (2LO-to-RF) isolation of for operating frequencies (LO, IF, RF=2.LO-IF) and the 40dB. influence of loads at spurious frequencies. For subharmonic mixer optimization, the dedicated small-signal Index Terms -Sub-harmonic Mixer, Cold FET, Lange mixer analysis implemented in CAD tools cannot be used coupler, Balun. since sub-harmonic mixers use half the 2nd LO harmonic to perform mixing. To overcome such a limitation, we have I. INTRODUCTIONdeveloped a specific CAD method enabling to derive the conversion matrix for the sub-harmonic operation of the Emerging millimeter-wave telecom applications such as transistor and to determine the optimum IF and RF loads for MWS (Multimedia Wireless Systems) imposes strict minimizing conversion losses. Mixers are inherently 3-port requirements on the output spectrum mask and on the non-linear devices. However, for small input signal, it is linearity of transmitters while necessitating the production possible to consider the mixer, pumped at a given LO level, of low-cost integrated circuits [1]. The up-converter mixer as a quasi-linear system [5] between its input and output constitutes one critical component with regard to system ports ( Fig. 1). performance. Key specifications of the mixer are a strong output rejection of the unwanted mixing frequencies and a high-linearity, which enables the mixer to be used at higher input power levels without adding distortion. In order to Access 1FI Access2 (RF) reach these goals, this work reports the development of a II(fJF) I2(fRF) specific design methodology dedicated to sub-harmonic > IY 4-cold FETs mixers [2] and the performances obtained at * pumped I 40GHz for a new balanced sub-harmonic MMIC in GaAs T PHEMT technology. Ych V2(fJF) V2(fRF) Yin II. SUB-HARMONIC MIXING PRINCIPLE The sub-harmonic mixing principle, which performs Optimal values of YRF, YIF and Lc mixing using the 2nd LO harmonic, shows better isolation properties than fundamental mixing, while requiring only ( II>A(y1 y2 V V1I half the LO frequency. To design a sub-harmonic mixer at12= millimeter-wave frequencies, an anti-parallel diod...