Lightweight cryptographic solutions are required to guarantee the security of Internet of Things (IoT) pervasiveness. Cryptographic primitives mandate a non-linear operation. The design of a lightweight, secure, non-linear 4 × 4 substitution box (S-box) suited to Internet of Things (IoT) applications is proposed in this work. The structure of the 4 × 4 S-box is devised in the finite fields GF (2 4 ) and GF ( (2 2 ) 2 ). The finite field S-box is realized by multiplicative inversion followed by an affine transformation. The multiplicative inverse architecture employs Euclidean algorithm for inversion in the composite field GF ( (2 2 ) 2 ). The affine transformation is carried out in the field GF (2 4 ). The isomorphic mapping between the fields GF (2 4 ) and GF ( (2 2 ) 2 ) is based on the primitive element in the higher order field GF (2 4 ). The recommended finite field S-box architecture is combinational and enables sub-pipelining. The linear and differential cryptanalysis validates that the proposed S-box is within the maximal security bound. It is observed that there is 86.5% lesser gate count for the realization of sub field operations in the composite field GF ( (2 2 ) 2 ) compared to the GF (2 4 ) field. In the PRESENT lightweight cipher structure with the basic loop architecture, the proposed S-box demonstrates 5% reduction in the gate equivalent area over the look-up-table-based S-box with TSMC 180 nm technology.

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Security of electronic data remains the major concern. The art of encryption to secure the data can beachieved in various levels of abstraction. The choice of the logic style in implementing the securityalgorithms has greater significance, and it can enhance the ability of providing better resistance to sidechannel attacks. The static CMOS logic style is proved to be prone to side channel power attacks. Theexploration of CMOS current mode logic style for resistance against these side channel attacks is discussedin this paper. Various characteristics of the current mode logic styles, which make it suitable for makingDPA resistant circuits are explored. A new methodology of biasing the sleep transistors of (MOS currentmode logic) MCML families is proposed. It uses pass gate transistors for power-gating the circuits. Thepower variations of the proposed circuits are compared against the standard CMOS counterparts. Logicgates such as XOR, NAND and AND gate structures of MCML families and static CMOS are designed andcompared for the ability of side channel resistance. A distributed arrangement of sleep transistors forreducing the static power dissipation in the logic gates is also proposed, designed and analyzed. All thelogic gates in MCML and CMOS were implemented using standard 180 nm CMOS technology employingCadence® EDA tools