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A 65nm NOR Flash technology, featuring a true 10λ², 0.042µm² cell, is presented for the first time for 1bit/cell and 2bit/cell products. Advanced 193nm lithography, floating gate self aligned STI, cobalt salicide and three levels of copper metallization allow the integration with a high density and high performance 1.8V CMOS. IntroductionThe continuous expansion and the evolution of wireless applications ask for increasing the density and the performances of Flash memories. In this paper we present a 65nm NOR Flash technology with a cell as small as 0.042µm² (0.021µm² per bit in multilevel memories), that is the smallest presented so far (1). Use of 193nm lithography with high NA, floating gate self aligned to STI isolation, cobalt salicide and three levels of copper interconnections allow us to keep following the 10λ² roadmap for NOR cell down to this generation, integrating for the first time at this technology node high performance logic for low voltage 1.8V operation suitable for System On Chip applications.

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