A b s t r a c t GaAs complementary FET logic structures have n+ and p+ doped areas separated by areas of semi-insulating (SI) GaAs. Such doped patterns form stray p -i -n double injection diodes which may cause latch-up. Using a SPICE equivalent circuit for the latch-up diodes, effect of latch-up on the performance of the logic gates has been simulated. This study shows that latch-up can severely affect the performance of the logic gates, and that the distance between the injecting contacts, back ground concentration of the S I material, and temperature are critical parameters in latch-up susceptibility.I. I n t r o d u c t i o n (:aAs complementary structures have inherent stray n+- SI-pS s(.riict,ures, or The n+ regioiis of the n-type device form cathodes, and the p+ regions of i.11e p t , y p e device form anodes; see Fig. 1. These logic gates iiiiiy, t,licrefore, suffer from strong current injection or latch-up efIvci,, especially for high levels of integration where the separation I)r(,wccn t,he two electrodes can be very small.In this paper, latch-up phenomenon in GaAs complementary structures is investigated, and its effect on complementary logic gnt,c performance is studied.
Circuit ModelSiiicr the characteristics of double injection diodes are similar to the Shockley diode, an equivalent circuit similar to the (:h30S latch-up circuit is used to simulate the performance of the si,ray p-i-11 diodes. In GaAs complementary structures, the semiiiisrilatiug region separating the p+ and the n+ areas is heavily coinpcnsated with a deep level acceptor (Mn or Cr) and a shallow donor (usually Sn). This compensation results in a slight p-(,,ype region which can be considered an n layer with respect to the p+ area and a p layer with respect to the n+ area. Dividing I.liis layer with a virtual line at the middle and considering the ])art close to the p+ area as an n-doped layer and the part close t,o the n+ area a.s a p-doped area, the double injection diode can t,lieii bc thought of as a p+npn+ four layer device, or Shockley tliode; sec Fig. l(b). The behavior of the double injection diode can, tlicrefore, be simulated using two bipolar junction transistors (DJT) and a resistor; see Fig. l(c). For a one-dimensional npn t.ransistor, the parameters are obtained from the formulas shown in references [4,5], where the common-emitter gain (neglecting surface recombination) and the transport saturation current The base-emitter and base-collector saturation currents, I,, and I,,., are obtained from the p -n saturation current relationships,For n+ -p junctions, p+ -n junctions, or short base transistors, this equation is appropriately modified [4]. Note that Ob and ae are the conductivities of the base and the emitter, wb is the base width, L, and L, are the diffusion lengths of electrons and holes, A, is the emitter area, q is the electronic charge, n, is the intrinsic carrier concentration, Db is the carrier diffusion constant in the base, NL is the concentration in the base per unit area, A is the junction area, D, and D...
