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This paper presents the DFT techniques used in Motorola's high perjormance e500 core, which implements the PowerPC "Book E" architecture and is designed to run at 600 MHz to I GHz. Highlights of the DFT features are atspeed logic built-in self-test (LBIST) for delay fault defection, very high test coverage for scan based at-speed deterministic delay-fault test patterns, 100% BIST for embedded memory arrays and 99.2% stuck-at fault test coverage for deterministic scan test patterns. A salient design feature is the isolation ring that facilitates testing of the core when if is integrated in an SoC or host processor.

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Several advances have been made in the Design for Testability of the MPC7400, the first fourth generation PowerPC microprocessor. The memory Array Built-In Self Test (ABIST) algorithms now support detecting write-recovery defects and more comprehensive diagnostics. Delay defects can be tested with scan patterns with the Phased Locked Loop (PLL) providing the at-speed launch-capture events. Several methodology and modeling improvements increased LSSD stuck-at fault test coverage. Design forManufacturability enhancements provide better tracking of initial silicon and fuse-based memory repair capabilities for improved yield and Time-to-Market.

In this paper we present the novel built-in delay fault test concepts incorporated intoMotorola's MPC7400 PowerPC microprocessor that allow us to use a slow speed tester to do at-speed, scan based, delay fault testing. A novel feature of the design is the programmable clock control circuit for issuing a given number of at-speed clocks for the delay test, once the test is initiated. Using transition and path delay fault test patterns, we have tested several MPC7400 chips at speed exceeding 540 MHz using tester speed of 63 MHz or lower.