DFT advances in the Motorola's MPC7400, a PowerPC/sup TM/ G4 microprocessor

Pyron, C.; Alexander, M.; Golab, J.; Joos, G.; Long, B.; Molyneaux, R.; Raina, R.; Tendolkar, N.

doi:10.1109/test.1999.805623

Cited by 24 publications

(5 citation statements)

References 16 publications

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“…Since CPUs are the major source of power consumption in DCSs [4], many microprocessor manufacturers including Intel, AMD, Motorolla and Transmeta have put a lot of effort into low-power processor design focusing on DVFS [15,[20][21][22]. DVFS is a promising energy saving technique that can be incorporated into scheduling; and many scheduling algorithms (e.g., [5,23]) using DVFS have been proposed for different problems.…”

Section: Scheduling In Hcssascheduling With Energy Consciousnessmentioning

confidence: 99%

On Effective Slack Reclamation in Task Scheduling for Energy Reduction

Lee¹,

Zomaya²

2009

Journal of Information Processing Systems

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Abstract:Power consumed by modern computer systems, particularly servers in data centers has almost reached an unacceptable level. However, their energy consumption is often not justifiable when their utilization is considered; that is, they tend to consume more energy than needed for their computing related jobs. Task scheduling in distributed computing systems (DCSs) can play a crucial role in increasing utilization; this will lead to the reduction in energy consumption. In this paper, we address the problem of scheduling precedence-constrained parallel applications in DCSs, and present two energy-conscious scheduling algorithms. Our scheduling algorithms adopt dynamic voltage and frequency scaling (DVFS) to minimize energy consumption. DVFS, as an efficient power management technology, has been increasingly integrated into many recent commodity processors. DVFS enables these processors to operate with different voltage supply levels at the expense of sacrificing clock frequencies. In the context of scheduling, this multiple voltage facility implies that there is a trade-off between the quality of schedules and energy consumption. Our algorithms effectively balance these two performance goals using a novel objective function and its variant, which take into account both goals; this claim is verified by the results obtained from our extensive comparative evaluation study.

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Section: Scheduling In Hcssascheduling With Energy Consciousnessmentioning

confidence: 99%

On Effective Slack Reclamation in Task Scheduling for Energy Reduction

Lee¹,

Zomaya²

2009

Journal of Information Processing Systems

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“…Like the MPC74xx microprocessors [3,5,7], the e500 core has implemented DFT features that supports at-speed delay fault testing using a tester that runs at much slower speeds than the microprocessor speed. Highlights of design The test is initiated by an asynchronous, non timing critical signal.…”

Section: Deterministic At-speed Delay Fault Testingmentioning

confidence: 99%

“…The design supports both broad side transition fault test patterns and path delay test patterns [3,5,7]. Several enhancements were made to the ATPG tool to support the at-speed clocking, improve ATPG run time and increase the test coverage for transition fault test patterns [7].…”

Section: Paper 211mentioning

confidence: 99%

Test methodology for Motorola's high performance e500 core based on PowerPC instruction set architecture

Bailey

Metayer

Svrcek

et al.

Proceedings. International Test Conference

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This paper presents the DFT techniques used in Motorola's high perjormance e500 core, which implements the PowerPC "Book E" architecture and is designed to run at 600 MHz to I GHz. Highlights of the DFT features are atspeed logic built-in self-test (LBIST) for delay fault defection, very high test coverage for scan based at-speed deterministic delay-fault test patterns, 100% BIST for embedded memory arrays and 99.2% stuck-at fault test coverage for deterministic scan test patterns. A salient design feature is the isolation ring that facilitates testing of the core when if is integrated in an SoC or host processor.

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“…The broad-side test structure is used to allow at-speed transition fault testing on the slower testers for Motorola microprocessor designs using PowerPC compliant instruction sets architecture [11,7]. A flexible clocking control was implemented in Motorola MPC7400 design to allow use of the PLL for issuing a variety of launch/capture events for broad-side transition test.…”

Section: Transition Test Needs Two Vectorsmentioning

confidence: 99%

Transition test generation using replicate-and-reduce transform for scan-based designs

Abadir

Zhu

Proceedings. 21st VLSI Test Symposium, 2003.

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In this paper, we presented a new transition ATPG methodology flow for scan-based design using broad-side test format. A Replicate and Reduce (RR) circuit transform is introduced, which maps the two time frame processing of transition fault ATPG to a single time frame processing on duplicated iterative blocks with reduced connection. A complete ATPG methodology flow is proposed to generate high coverage transition test patterns both fast and efficiently. Experimentation results on several circuits from next generation Motorola microprocessor design are presented to show the effectiveness of our approach.

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DFT advances in the Motorola's MPC7400, a PowerPC/sup TM/ G4 microprocessor

Cited by 24 publications

References 16 publications

On Effective Slack Reclamation in Task Scheduling for Energy Reduction

On Effective Slack Reclamation in Task Scheduling for Energy Reduction

Test methodology for Motorola's high performance e500 core based on PowerPC instruction set architecture

Transition test generation using replicate-and-reduce transform for scan-based designs

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