Test methodology for Motorola's high performance e500 core based on PowerPC instruction set architecture

Bailey, B.; Metayer, A.; Svrcek, B.; Tendolkar, N.; Wolf, E.; Fiene, E.; Alexander, M.; Woltenberg, R.; Raina, R.

doi:10.1109/test.2002.1041808

Cited by 16 publications

(15 citation statements)

References 9 publications

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“…Transition fault test application is being widely carried out in industry [1,8,10,12,19]. In [1], methods for at-speed built-in self test (BIST) and deterministic test are presented.…”

Section: Prior Workmentioning

confidence: 99%

“…In [1], methods for at-speed built-in self test (BIST) and deterministic test are presented. The methods achieve high fault coverage, however, they require strict restrictions on the circuit design, including no multicycle paths and no X-states.…”

Section: Prior Workmentioning

confidence: 99%

“…At-speed manufacturing test based on automatic test pattern generation (ATPG) is therefore becoming popular as a means to exercise circuit logic at-speed with high fault coverage [1,12]. The transition fault model is used to generate delay fault test patterns for the IC.…”

Section: Introductionmentioning

confidence: 99%

“…These are applied at-speed to detect delay defects that cause slow transitions on internal logic. Since ATE cannot pulse capture clocks on internal flipflops at functional speeds, the IC's functional clocks are used for test response capture [1]. At-speed test has been used at IBM ASICs since 2003; clocks generated by PLLs have been used for functional release-capture 1 .…”

Section: Introductionmentioning

confidence: 99%

“…The novel contributions of this work are as follows. 1. The proposed methodology is highly scalable to any number of logic domains-under-test.…”

Section: Introductionmentioning

confidence: 99%

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At-Speed Structural Test For High-Performance ASICs

Iyengar

Yokota²,

Yamada³

et al. 2006

2006 IEEE International Test Conference

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At-speed test of integrated circuits is becoming critical to detect subtle delay defects. Existing structural at-speed test methods are inadequate because they are unable to supply sufficiently-varied functional clock sequences to test complex sequential logic. Moreover, they require tight restrictions on the circuit design. In this paper, we present a new method for at-speed structural test of ASICs, having no tight restrictions on the circuit design. In the present implementation, any complex at-speed functional clock waveform for 16 cycles can be applied. We present DFT structures that can generate high-speed launch-off-capture as well as launch-offscan clocking without the need to switch a scan enable atspeed. We also describe a method to test asynchronous clock domains simultaneously. Experimental results on fault coverage and hardware measurements for three multi-million gate ASICs demonstrate the feasibility of the proposed approach.

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“…Transition fault test application is being widely carried out in industry [1,8,10,12,19]. In [1], methods for at-speed built-in self test (BIST) and deterministic test are presented.…”

Section: Prior Workmentioning

confidence: 99%

Section: Prior Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

“…The novel contributions of this work are as follows. 1. The proposed methodology is highly scalable to any number of logic domains-under-test.…”

Section: Introductionmentioning

confidence: 99%

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At-Speed Structural Test For High-Performance ASICs

Iyengar

Yokota²,

Yamada³

et al. 2006

2006 IEEE International Test Conference

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Bottom-up approach in automated embedded memory model generation for high-performance microprocessors

Bhadra¹,

Abadir²,

Burgess³

et al. 2006

IEE Proc., Comput. Digit. Tech.

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Design For At-Speed Structural Test And Performance Verification Of High-Performance ASICs

Iyengar

Johnson

Anemikos

et al. 2006

IEEE Custom Integrated Circuits Conference 2006

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in high-performance designs, a large fraction of the total numPerformance verification is critical to high-performance ber of paths after timing closure are now critical [12]. Hence, ASICs manufacturing. Performance verification ensures that an automatic test pattern generation (ATPG) tool that produces only those chips whose performance is higher than an adver-high transition fault coverage is guaranteed to exercise a large tised threshold are shipped to demanding customers. This pro-number of the critical paths in the design. At-speed transition vides a means to weed out nominal performance ASICs, and fault test with high coverage can therefore be used as a lowalso ship ASICs at difference grades. At-speed structural test cost platform for performance verification. can provide performance verification capability at very low In this paper, we present a new methodology for perforcost. In this paper, we present a scalable and flexible struc-mance verification of high-performance ASICs using at-speed tural test methodfor performance verification of ASICs. The structural test (ASST). The novel contributions of this work are tural tet methodfor perormance erlficalonasffollows.h proposed method requires no tight restrictions on the circuit as follows design. Moreover, low-cost testers are used, thus sharply re-1. The proposed methodology is highly scalable to any number ducing test cost. of logic domains-under-test. Any number of on-chip phase-1

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Test methodology for Motorola's high performance e500 core based on PowerPC instruction set architecture

Cited by 16 publications

References 9 publications

At-Speed Structural Test For High-Performance ASICs

At-Speed Structural Test For High-Performance ASICs

Bottom-up approach in automated embedded memory model generation for high-performance microprocessors

Design For At-Speed Structural Test And Performance Verification Of High-Performance ASICs

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