At-speed test of integrated circuits is becoming critical to detect subtle delay defects. Existing structural at-speed test methods are inadequate because they are unable to supply sufficiently-varied functional clock sequences to test complex sequential logic. Moreover, they require tight restrictions on the circuit design. In this paper, we present a new method for at-speed structural test of ASICs, having no tight restrictions on the circuit design. In the present implementation, any complex at-speed functional clock waveform for 16 cycles can be applied. We present DFT structures that can generate high-speed launch-off-capture as well as launch-offscan clocking without the need to switch a scan enable atspeed. We also describe a method to test asynchronous clock domains simultaneously. Experimental results on fault coverage and hardware measurements for three multi-million gate ASICs demonstrate the feasibility of the proposed approach.

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in high-performance designs, a large fraction of the total numPerformance verification is critical to high-performance ber of paths after timing closure are now critical [12]. Hence, ASICs manufacturing. Performance verification ensures that an automatic test pattern generation (ATPG) tool that produces only those chips whose performance is higher than an adver-high transition fault coverage is guaranteed to exercise a large tised threshold are shipped to demanding customers. This pro-number of the critical paths in the design. At-speed transition vides a means to weed out nominal performance ASICs, and fault test with high coverage can therefore be used as a lowalso ship ASICs at difference grades. At-speed structural test cost platform for performance verification. can provide performance verification capability at very low In this paper, we present a new methodology for perforcost. In this paper, we present a scalable and flexible struc-mance verification of high-performance ASICs using at-speed tural test methodfor performance verification of ASICs. The structural test (ASST). The novel contributions of this work are tural tet methodfor perormance erlficalonasffollows.h proposed method requires no tight restrictions on the circuit as follows design. Moreover, low-cost testers are used, thus sharply re-1. The proposed methodology is highly scalable to any number ducing test cost. of logic domains-under-test. Any number of on-chip phase-1

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