Analysis of Timing Failures Due to Random AC Defects in VLSI Modules

Tendolkar, N.

doi:10.1109/dac.1985.1586020

Cited by 40 publications

(6 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…l and 0.04 in the experiments. This exponential distribution for defect size (given that defects occur) has been studied in many publications [ 19,201 and is a practical assumption to be used. Note that it is also possible to adopt other distributions.…”

Section: Defect Distributionmentioning

confidence: 99%

On theoretical and practical considerations of path selection for delay fault testing

Liou¹,

Wang²,

Cheng³

IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002.

View full text Add to dashboard Cite

In current industrial practice, critical path selection is an indispensable step for AC delay test and timing validation. Traditionally, this step relies on the construction of a set of worse-case paths based upon discrete timing models. The assumption of discrete timing models can be invalidated by delay effects in the deep submicron domain, where timing defects and process variation are statistical in nature. In this paper, we study the problem of optimizing critical path selection, under both fixed delay and statistical delay assumptions. With a novel problem formulation and new theoretical results, we prove that the problem in both cases are computationally intractable. We then discuss practical heuristics and their theoretical pe formance bounds, and demonstrate that among all heuristics under consideration, only one is theoretically feasible. Finally, we provide consistent experimental results based upon defect-injected simulation using an eficient statistical timing analysis framework

show abstract

Section: Defect Distributionmentioning

confidence: 99%

On theoretical and practical considerations of path selection for delay fault testing

Liou¹,

Wang²,

Cheng³

IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002.

View full text Add to dashboard Cite

show abstract

“…The defect size was of exponential distribution λ λ * * t e − [7], with 3 . 0 = λ and ¥ =0.1 in our experiment ( λ can be determined experimentally from measurement data in practice, whose inverse is the weighted average delay defect size.).…”

Section: Experimental Studymentioning

confidence: 99%

“…In Deep Sub-Micron technology (DSM), commonly observed failure mechanisms such as resistive opens in vias and interconnects, gate oxide punch through, etc, can all lead to excessive delays on signal paths [7] [9]. There is growing concern [3] that many of these small delay defects that often escape detection at test do not accelerate sufficiently in burn-in to be detected, and can cause reliability problems in the field.…”

Section: Introductionmentioning

confidence: 99%

Reduce Yield Loss in Delay Defect Detection in Slack Interval

Yan

Singh

13th Asian Test Symposium

View full text Add to dashboard Cite

1 A new delay-testing scheme that identifies abnormal delays in the slack interval by comparing switching delays in neighboring dies on a wafer has been recently proposed and validated on experimental circuits. The simulation showed orders of magnitude delay defect detection efficiency improvement. In this paper we investigated the yield loss problem and proposed a practical production test based on delay defect detection in slack interval (DDSI).

show abstract

“…The standard deviation ox of a path can be assumed approximately constant in large circuits [7]. Therefore, in a timingoptimized design, every path has the same mean path delay, the same standard deviation, and the same density function.…”

Section: Clock Rate and Path Delav Sensitivitymentioning

confidence: 99%

“…Since the value p is generally low, the probability that the path under test has more than one delay defect is extremely low [7]. Thus, it can be further assumed that every path can have at most one delay defect.…”

Section: Manufacturing Yield and Defect Level In A Timing-odtimized Dmentioning

confidence: 99%

Delay Testing Quality in Timing-Optimized Designs

Park¹,

Underwood²,

Williams³

et al.

1991, Proceedings. International Test Conference

View full text Add to dashboard Cite

As electronic CAD synthesis tools become more powerful, they will increasingly refine delay measiirements and adjust path delays so as to increase the clock rate or to reduce the chip area. This paper discusses the implications of such events on testing for delay defects. We provide a timing optimization procedure and show that the resultant density function of path delays is a delta function. Finally, we discuss the impact of timing optimization on the yield of a manufacturing process and the defect level for delay faults.

show abstract

Analysis of Timing Failures Due to Random AC Defects in VLSI Modules

Cited by 40 publications

References 0 publications

On theoretical and practical considerations of path selection for delay fault testing

On theoretical and practical considerations of path selection for delay fault testing

Reduce Yield Loss in Delay Defect Detection in Slack Interval

Delay Testing Quality in Timing-Optimized Designs

Contact Info

Product

Resources

About