This paper presents an efficient delay test generation system for combinational logic circuits. Delay testing problems are divided into gross delay fault testing and small delay fault testing in order to explore the trade-off between the levels of delay testing effort and the confidence levels of proper system operation. Complete automatic test pattern generation algorithms are proposed for both gross delay faults and small delay faults. Especially for the small delay fault test generation, new search space enumeration techniques are employed so as to bias the search space such that a delay test for relatively long paths can be found. Also a novel timing analysis method via functionality check is presented for delay test generation. Finally, complete test results are demonstrated for both gross delay faults and small delay faults on several benchmark circuits.

As electronic CAD synthesis tools become more powerful, they will increasingly refine delay measiirements and adjust path delays so as to increase the clock rate or to reduce the chip area. This paper discusses the implications of such events on testing for delay defects. We provide a timing optimization procedure and show that the resultant density function of path delays is a delta function. Finally, we discuss the impact of timing optimization on the yield of a manufacturing process and the defect level for delay faults.

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