An efficient delay test generation system for combinational logic circuits

Abstract

This paper presents an efficient delay test generation system for combinational logic circuits. Delay testing problems are divided into gross delay fault testing and small delay fault testing in order to explore the trade-off between the levels of delay testing effort and the confidence levels of proper system operation. Complete automatic test pattern generation algorithms are proposed for both gross delay faults and small delay faults. Especially for the small delay fault test generation, new search space enumeration techniques are employed so as to bias the search space such that a delay test for relatively long paths can be found. Also a novel timing analysis method via functionality check is presented for delay test generation. Finally, complete test results are demonstrated for both gross delay faults and small delay faults on several benchmark circuits.

A GPU-Based Fault Simulator for Small-Delay Faults

“…Small delay fault refers to the fault whose size is smaller than a clock cycle. It is opposite to gross delay (gross delay refers to the fault whose size is greater than a clock cycle [1]). The conditions for small delay fault can be detected is that fault size must be larger than the sensitized path time margin ( slack ) value, namely the difference of the test clock period minus the path delay [1].…”

“…truthtbl [1][0]=0.For nand-gate of three inputs(gut->fn=1),if the input are 1,1,0.FirstLy, according to the first input 1, we search truthtbl and find result is val=truthtbl [1][1]=0. Secondly, according to the second input 1,we search truthtb2 and obtain the result is truthtb2 [1][0][1](val=0)=1.…”

“…truthtbl [1][0]=0.For nand-gate of three inputs(gut->fn=1),if the input are 1,1,0.FirstLy, according to the first input 1, we search truthtbl and find result is val=truthtbl [1][1]=0. Secondly, according to the second input 1,we search truthtb2 and obtain the result is truthtb2 [1][0][1](val=0)=1. Finally, according to the third input 0,we search truthtb2 and obtain the result is truthtb2 [1][1][0](at this monment val is 1)=1.Then we get the final result.…”

“…Secondly, according to the second input 1,we search truthtb2 and obtain the result is truthtb2 [1][0][1](val=0)=1. Finally, according to the third input 0,we search truthtb2 and obtain the result is truthtb2 [1][1][0](at this monment val is 1)=1.Then we get the final result.…”

Small Delay Fault Simulation for Sequential Circuits

“…A delay fault is called a gross delay fault if its delay defect size is greater than the system clock interval. Otherwise, a delay fault is called a small delay fault [1].…”