No abstract

FIVE-VOLT ONLY OPERATION is now an industry standard for electrically erasable and programmable nonvolatile memories.A 4K nonvolatile static RAM (NVRAM) with on-chip high-voltage generation and regulation was designed with high density and future scalability as key design parameters. Using wafer stepper HMOs I dual poly FLOTOX' technology and a restructured cell, a die size of 30,268 mils2 (19.53mm2) was achieved: Figure 1. Single pulses control the data transfers: STORE (static RAM t o E2PROM) and RECALL (EQPROM to static RAM).Typical electrical characteristics are shown in Table 1.The array cell is a nine-transistor structure consisting of a standard six transistor depletion load static RAM cell, an E* PROM transistor, and two additional transistors used as gating devices: Figure 2. While a smaller cell is possible, the gating devices are necessary t o eliminate the dc current path from the high voltage source.The STORE operation occurs in two-timed lOms steps.During the first half of the STORE cycle, the entire E* PROM array is erased to a low threshold by holding the CLK and PRO lines at zero volts and raising the CLR line t o the internally generated high voltage (VPP). During the second half of the cycle, CLR is lowered t o zero volts, CLK is set to VCC and PRO to VPP. Diode connected transistor T9 enables node D to retain high voltage by trapping charge when the CLR line is lowered from VPP t o zero volts. The state of the static RAM cell determines whether the transfer gate controlled by CLK is conducting, which discharge the trapped charge on node D, or nonconduo ting which leaves the trapped charge intact. The former condition causes the E2 element t o program, the latter, to inhibit programming, which leaves the E2 element erased. The state of the RAM cell is thereby stored in the E2 element. ray power supply (VVD). The static RAM depletion loads have an inbalance to allow the RAM cell to latch in a desired state during VDD ramping. During RECALL, the CLK, PRO, and CLR lines are held high, and VDD is ramped to ground and back to VCC. The E' element determines the state of the static RAM cell during the ramping. A high threshold, or programmed, E2 element is nonconductive and allows the imbalance on the loads to be dominant; a low threshold, or erased, E' element is conductive and overcomes the imbalance of the loads, pulling the static RAM cell to the opposite state. Typical waveforms for STORE and RECALL sequencing are shown in Figures 3 and 4. RECALL data transfers requires complex sequencing of high (VPP) and low (VCC) voltages. Since the design required TTL The RECALL operation requires control of the internal ar-The proper operation of the cell during STORE and ~ tile Memory," ISSCC DIGEST OF TECHNICAL PAPERS,p.l52; 'Johnson, W., et. al., "A 1 6 K b Electrically Erasable Nonvola-Feb., 1980. level signals to initiate STORE and RECALL operations, these complex control functions were integrated on chip. A singlecontrol pin differentiates between standard static RAM operation and nonvolatile (STORE/RE...