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Ultra-low voltage digital circuit design is an active research area, especially for portable applications such as wearable electronics, intelligent remote sensors, implantable medical devices, and energy-harvesting systems. Due to their application scenarios and circuit components, two major goals for these systems are minimizing energy consumption and improving compatibility with low-voltage power supplies and analog components. The most effective solution to achieve these goals is to reduce the supply voltage, which, however, raises the issue of operability. At ultra-low supply voltages, the integrity of digital signals degrades dramatically due to the indifference between active and leakage currents. In addition, the system timing becomes more unpredictable as the impact of process and supply voltage variations being more significant at lower voltages. This paper presents a comparative study among three techniques for designing digital circuits operating at ultra-low voltages, i.e., Schmitt-triggered gate structure, delayinsensitive asynchronous logic, and Fully-Depleted Silicon-on-Insulator technology. Results show that despite the tradeoffs, all eight combinations of these techniques are viable for designing ultra-low voltage circuits. For a given application, the optimum circuit design can be selected from these combinations based on the lowest voltage, the dynamic range, the power budget, the performance requirement, and the available semiconductor process node.

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The fixed-point binary representation, an integer Correction (ODAC) in order to produce useful results under format with an implied binary point, is an alternative to the overflow conditions. Because multiplication among fixed-IEEE floating-point binary layout. Systems that do not support point numbers is more prone to overflow than other basic the IEEE floating-point format, e.g., mobile devices, use the arithmetic operations, this paper describes a fixed-point fixed-point format because it fits well into integer data paths multiplier using ODAC.whereas floating-point requires its own data path. Software Mult usingtoDAC.developers who port to fixed-point systems often face issues when Mostcapplicatins r ntfixed-pointn s usin balancing range and precision. Those issues, overflow and large 2's-complement integers and define the binary point's position rounding errors, often arise from arithmetic operations, making prior to runtime. The position of the binary point determines debugging more difficult. The proposed solution limits hardware the power of two of each bit; the bits before the binary point support to a set of fixed-point formats and adjusts the format of are positive powers of two starting from zero while the bits the output based on the user supplied format and overflow. The after the binary point are negative powers of two starting from format of the result is readjusted on overflow in order to return a negative one. To help describe the binary point position of a useful result but with the sacrifice of precision. In addition to the fixed-point integer, the Q-notation, QIF, states that a binary corrected result, the overflow flag is raised so the software and subsequent logic are aware of the readjustment in the result's number contains I integer bits and F fractional bits, which may format. This work has been implemented in a fixed-point not add up to the total number of bits in the number. In this multiplier because multiplication yields the largest overflow paper, the Q-notation counts all the bits, including the sign bit, among the four basic arithmetic operations. In order to detect so that the sum of I and F equals the bit-width of the binary overflow early, the fixed-point multiplier adopts preliminary number. overflow detection. With the idea of taking the burden of fixedMultiplying two operands of the same integer format point scaling off of the programmer, the fixed-point multiplier naturally yields a result that is double the bit-width than the with overflow detection and correction provides a starting point operands. The same is true for fixed-point numbers; if the towards mitigating fixed-point errors.operands are both QIF, the product will be Q(21).(2F). In the case of mixed-format multiplication where one operand is