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A simple yet effective approach to improve the linearity of the transconductor-capacitor (Gm−C) filters is proposed without any area or power overhead. Following a generalized nodal analysis, the transconductors of classical filter topology are rewired such that their input differential voltage lies within the linear regime. The effectiveness of the proposed method is validated through the design and simulation of a fifth-order Butterworth low-pass filter (LPF) in a standard 65-nm CMOS process. The proposed filter implementation occupies 0.0164 mm 2 (0.003 mm 2 /pole) die area and consumes 167-µW for the cut-off frequency of 1-MHz. Operating at 1-V voltage supply, it shows an in-band total harmonic distortion (THD) of −49.14 dB for 200-mV peak-to-peak 1MHz differential voltage. An in-band 3rd-order intercept point (IIP3) of 9.36 dBm is also achieved with an in-band spurious-free-dynamic range (SFDR) greater than 53-dB, all of which reflect meaningful improvements relative to the classical architecture and despite the modest linearity performance of the internal Gm stages.INDEX TERMS Analog filter, Butterworth approximation, complementary metal-oxide-semiconductor (CMOS), continuous-time, Gm−C, linearity, low-pass filter, low-power, operational transconductance amplifier (OTA), and signal flow graph (SFG).

When designing a system-on-chip (SOC), a network-on-chip (NOC) paradigm is the backbone of used interconnection, but in recent years, with a great improvement in silicon technology and the ability to implement billions of transistors on a wafer, it sounds that wire-based communication is not efficient any longer, therefore designers intend to replace wireless transferring data methodology instead. In the following, we show how the performance of the wireless network is improved with subnet extension. This paper focuses on the evaluation of delay and throughput which are two important factors in network proficiency. In fact, to enhance the performance of the system, we need to reduce the number of delay cycles and improve the throughput, therefore to keep balance between these two parameters, designer has to adjust the packet injection rate (PIR) in a safe margin such that it does not exceed a certain point in each state, otherwise delay is uncontrollable, thus it is required to clearly identify the take-off points. About the designer also has to be informed purpose for which the system is going to be designed. It strictly depends on whether high throughput or low delay cycle is desirable. Subnet extension is a way to achieve this target. Here, totally three networks with the number of cores 64, 512 and 1024 have been selected, respectively. The effect of subnet extension is evaluated on each one. The behavior of each network with different number of subnets and IPs is studied. Obtained results from the simulator for different ranges of PIR and subnets are significant. To emphasize, we highlight the take-off points for the delay cycles and the points which does not cross the PIR level. Performance evaluation is conducted based on flit-accurate and open source system C simulator BookSim.