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Matrix computations are very important in image processing applications. Processing large images or matrices is computationally intensive, power hungry and requires a large amount of memory. This paper discusses the hardware implementation of a factorisation based approach for Haar wavelet transform (HWT) on reconfigurable hardware using distributed arithmetic (DA) principles. The proposed architectures can be integrated into a multiresolution based system for automatic detection and segmentation of tumour in medical images. Two factorisation methodologies are presented and their impact on FPGA implementation is addressed in terms of different resources required and performance achieved.

Processing large images requires a large amount of memory, power hungry and computationally intensive which causes a high demand for an efficient algorithm implementation to overcome the problems. This paper discusses an efficient hardware implementation of the Haar wavelet transform (HWT) core on reconfigurable platforms. The proposed HWT implementation can be explored for automatic detection and segmentation of tumour in medical images. The HWT algorithm has been demonstrated for the segmentation of phantom data and its hardware implementation has been carried out using Handel C on different field programmable gate arrays (FPGAs) devices. Results obtained for the implementation performance in terms of area and power have been evaluated and compared with other existing systems for HWT computation.

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