This paper presents a CMOS floating and tunable capacitance multiplier with a very large multiplication factor. The proposed design uses CCII and OTAs designed using MOSFETs biased in subthreshold region to provide low power consumption and high multiplication factor. TANNER TSPICE simulation tool is used to confirm the functionality of the design in 0.18µm TSMC CMOS technology. The circuit is powered using ±0.75V DC supply voltage. Simulation results indicate that the maximum multiplication factor is 3600 and the maximum error is 8.6%.

A CMOS rectifier for RF energy harvesting is proposed. The structure of the proposed design is based on a modified cross-coupled architecture. It employs an adaptive body biasing technique to lower the transistor threshold voltage (Vth) when the PMOS is ON which increases the conduction current. On the other hand, this technique increases Vth when the PMOS is OFF to minimize the current flowing in the reverse bias condition. The proposed design is simulated using 0.18µm TSMC CMOS technology under various loading conditions and input frequency of 953 MHz. A peak power conversion efficiency (PCE) of 78.2% is achieved at an input power of -27.5 dBm and a 100 kΩ load.INDEX TERMS CMOS rectifier, RF energy harvesting, body biasing, power conversion efficiency (PCE).

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