We report on the microscopic structure of the SiOx layer and the transport mechanism in polycrystalline Si (poly-Si) passivated contacts, which enable high-efficiency crystalline Si (c-Si) solar cells. Using electron beam induced current (EBIC) measurements, we accurately map nanoscale conduction-enabling pinholes in 2.2 nm thick SiOx layers in a poly-Si/SiOx/c-Si stack. These conduction enabling pinholes appear as bright spots in EBIC maps due to carrier transport and collection limitations introduced by the insulating 2.2 nm SiOx layer. Performing high-resolution transmission electron microscopy at a bright spot identified with EBIC reveals that conduction pinholes in SiOx can be regions of thin tunneling SiOx rather than a geometric pinhole. Additionally, selectively etching the underlying poly-Si layer in contacts with 1.5 and 2.2 nm thick SiOx layers using tetramethylammonium hydroxide results in pinhole-like etch features in both contacts. However, EBIC measurements for a contact with a thinner, 1.5 nm SiOx layer do not reveal pinholes, which is consistent with uniform tunneling transport through the 1.5 nm SiOx layer. Finally, we theoretically show that reducing the metal to the c-Si contact size from microns, like in the p-type passivated emitter rear contact, to tens of nanometers, like in poly-Si contacts, allows lowering of the unpassivated contact area by several orders of magnitude, thus resulting in excellent passivation, as has been demonstrated for these contacts.
High-efficiency crystalline silicon (Si) solar cells require textured surfaces for efficient light trapping. However, passivation of a textured surface to reduce carrier recombination is difficult. Here, we relate the electrical properties of cells fabricated on a KOH-etched, random pyramidal-textured Si surface to the nanostructure of the passivated contact and the textured surface morphology. The effects of both microscopic pyramidal morphology and nanoscale surface roughness on passivated contacts consisting of polycrystalline Si (poly-Si) deposited on top of an ultrathin, 1.5−2.2 nm, SiO x layer are investigated. Using atomic force microscopy, we show a pyramid face, which is predominantly a Si(111) plane to be significantly rougher than a polished Si(111) surface. This roughness results in a nonuniform SiO x layer as determined by transmission electron microscopy of a poly-Si/SiO x contact. Our device measurements also show an overall more resistive and hence a thicker SiO x layer over the pyramidal surface as compared to a polished Si(111) surface, which we relate to increased surface roughness. Using electron-beam-induced current measurements of poly-Si/SiO x contacts, we further show that the SiO x layer near the pyramid valleys is preferentially more conducting and hence likely thinner than over pyramid tips, edges, and faces. Hence, both the microscopic pyramidal morphology and nanoscale roughness lead to a nonuniform SiO x layer, thus leading to poor poly-Si/SiO x contact passivation. Finally, we report >21% efficient and ≥80% fill-factor front/back poly-Si/SiO x solar cells on both single-side and double-side textured wafers without the use of transparent conductive oxide layers, and show that the poorer contact passivation on a textured surface is limited to boron-doped poly-Si/SiO x contacts.
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