Thermography enables non-invasive, accessible, and easily repeated foot temperature measurements for diabetic patients, promoting early detection and regular monitoring protocols, that limit the incidence of disabling conditions associated with diabetic foot disorders. The establishment of this application into standard diabetic care protocols requires to overcome technical issues, particularly the foot sole segmentation. In this work we implemented and evaluated several segmentation approaches which include conventional and Deep Learning methods. Multimodal images, constituted by registered visual-light, infrared and depth images, were acquired for 37 healthy subjects. The segmentation methods explored were based on both visual-light as well as infrared images, and optimization was achieved using the spatial information provided by the depth images. Furthermore, a ground truth was established from the manual segmentation performed by two independent researchers. Overall, the performance level of all the implemented approaches was satisfactory. Although the best performance, in terms of spatial overlap, accuracy, and precision, was found for the Skin and U-Net approaches optimized by the spatial information. However, the robustness of the U-Net approach is preferred.

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Infrared thermography is a non-invasive and accessible tool that maps the surface temperature of a body. This technology is particularly useful for diabetic foot disorders, since it facilitates the identification of higher risk patients by frequent monitoring and therefore limits the incidence of disabling conditions. The aim of this work is to provide a methodology to explore the entire plantar aspects of both feet, based on infrared thermography, for the assessment of diabetic foot anomalies. A non-invasive methodology was established to identify areas of higher risk and track their progress via longitudinal monitoring. A standard morphological model was extracted from a group of healthy subjects, nine females and 13 males, by spatial image registration. This healthy foot model can be taken as a template for the assessment of temperature asymmetry, even in cases in which partial amputations or deformations are present. A pixel-wise comparison of the temperature patterns was carried out by Wilcoxon´s matched-pairs test using the corresponding template. For all the subjects, the left foot was compared to the contralateral foot, the right one, providing a map of statistically significant areas of variation, within the template, among the healthy subjects at different time points. In the female case, the main areas of variability were the boundaries of the feet, whereas for the male, in addition to this, substantial changes that exhibited a clear pattern were observed. A fast and simple monitoring tool is provided to be used for personalized medical diagnosis in patients affected by diabetic foot disorders.

Currently, high-level synthesis (HLS) methods and tools are a highly relevant area in the strategy of several leading companies in the field of system-on-chips (SoCs) and field programmable gate arrays (FPGAs). HLS facilitates the work of system developers, who benefit from integrated and automated design workflows, considerably reducing the design time. Although many advances have been made in this research field, there are still some uncertainties about the quality and performance of the designs generated with the use of HLS methodologies. In this paper, we propose an optimization of the HLS methodology by code refactoring using Xilinx SDSoCTM (Software-Defined System-On-Chip). Several options were analyzed for each alternative through code refactoring of a multiclass support vector machine (SVM) classifier written in C, using two different Zynq®-7000 SoC devices from Xilinx, the ZC7020 (ZedBoard) and the ZC7045 (ZC706). The classifier was evaluated using a brain cancer database of hyperspectral images. The proposed methodology not only reduces the required resources using less than 20% of the FPGA, but also reduces the power consumption −23% compared to the full implementation. The speedup obtained of 2.86× (ZC7045) is the highest found in the literature for SVM hardware implementations.

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