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The reuse of intellectual property (IP) cores within systems offers significant potential to increase design producreconfigurable computing systems is a promising approach for tivity. improving the productivity of reconfigurable system design.Reuse of intellectual property (IP) cores, however, is diffiFurther, there are a large variety of reusable IP cores available for cult. Reusing a digital circuit within an RC system requires a variety of application-specific functions. These cores, however, t-desig a 1) Slect the an RCuit re,u2e are created from different design tools and are difficult to the designer to: 1) Select the appropriate circuit core, 2) integrate into a single reconfigurable system design. To facilitate understand the details of the core, 3) create interface circuitry the reuse of these cores, an XML schema has been created for to integrate the core into the system, and 4) verify the core representing the essential details of a core in a reconfigurable within the system. One study suggested that reuse was not computing design environment, This paper presenats this XML computing~dsgeniomt. Thspprpeet hsXL cost effective unlless the cost of integrating the core within a schema and describes how it can be used to facilitate reuse in reconfigurable computing systems.

Reconfigurable computing systems remain difficult to use and program. One way to increase design productivity for these systems is through reuse of previously developed and verified intellectual property (IP) cores. This paper presents CHREC XML, a XML schema that facilitates IP reuse by encapsulating the details of reusable IP cores at multiple levels of abstraction. This schema is independent from any design language or tool and can be used by any tool to understand many details about the interface of a reusable circuit. An IP integration tool was also created based on this schema to demonstrate the ease of IP reuse when cores are described in this meta-data description. This IP integration tool allows a designer to easily select and integrate IP cores from a variety of languages/tools and automatically run the appropriate tools to generate the cores in a form usable by downstream implementation tools.

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