A multi-layered XML schema and design tool for reusing and integrating FPGA IP

Arnesen, Adam; Rollins, Nathaniel; Wirthlin, Michael

doi:10.1109/fpl.2009.5272468

Cited by 8 publications

(3 citation statements)

References 4 publications

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“…Wirthlin et al [10] used XML to describe common IP block elements and defined their own schema using IP-XACT syntax. They proposed a lightweight version intended for Reconfigurable Computing (RC) systems, such as interface specifications and capturing HLLs data types information.…”

Section: Related Workmentioning

confidence: 99%

IP-XACT extensions for Reconfigurable Computing

Nane

Haastregt

Stefanov

et al. 2011

ASAP 2011 - 22nd IEEE International Conference on Application-Specific Systems, Architectures and Processors

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Many of today's embedded multiprocessor systems are implemented as heterogeneous systems, consisting of hardware and software components. To automate the composition and integration of multiprocessor systems, the IP-XACT standard was defined to describe hardware IP blocks and (sub)systems. However, the IP-XACT standard does not provide sufficient means to express Reconfigurable Computing (RC) specific information, such as Hardware dependent Software (HdS) meta-data, which prevents automated integration. In this paper, we propose several IP-XACT extensions such that the HdS can be generated and integrated automatically. We validate these specific extensions and demonstrate the interoperability of the approach based on an H.264 decoder application case study. For this case study we achieved an overall 30.4% application-wise speed-up and we reduced the development time of HdS from days to a few seconds.

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Section: Related Workmentioning

confidence: 99%

IP-XACT extensions for Reconfigurable Computing

Nane

Haastregt

Stefanov

et al. 2011

ASAP 2011 - 22nd IEEE International Conference on Application-Specific Systems, Architectures and Processors

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“…XML has also been used in the context of hardware de- scription, for instance as intermediate language to carry out HDL code transformations [9] or to specify low level structural descriptions [10]. An approach closer to the work described here is[ll], [12] where XML is used for interface specification to improve the reusability of cores in reconfigurable platforms. This approach uses XML to generate HDL wrappers for cores that are described in different languages or can even be generated from different tools.…”

Section: Introductionmentioning

confidence: 99%

Improving Hardware Reuse through XML-based Interface Encapsulation

S'nchez

López‐Vallejo

Iglesias

et al. 2012

2012 IEEE 17th International Conference on Engineering of Complex Computer Systems

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This work proposes an encapsulation scheme aimed at simplifying the reuse process of hardware cores. This hardware encapsulation approach has been conceived with a twofold objective. First, we look for the improvement of the reuse interface associated with the hardware core description. This is carried out in a first encapsulation level by improving the limited types and configuration options available in the conventional HDLs interface, and also providing information related to the implementation itself. Second, we have devised a more generic interface focused on describing the function avoiding details from a particular implementation, what corresponds to a second encapsulation level. This encapsulation allows the designer to define how to configure and use the design to implement a given functionality. The proposed encapsulation schemes help improving the amount of information that can be supplied with the design, and also allow to automate the process of searching, configuring and implementing diverse alternatives.

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“…En [ARW09] se describen las posibilidades de manipulación de los cores encapsulados utilizando el XML-Schema: GUI para la selección de cores en una biblioteca de componentes independientemente del lenguaje en el que se describa el core, cambio en la configuración de los parámetros, generación de un wrapper del core seleccionado y configurado, por ejemplo VHDL. El core junto con el wrapper generado están listos para ser integrados en un sistema.…”

Section: Xml Para El Encapsulado De Hardwareunclassified

Implementación de Algoritmos de Procesado de Señal sobre FPGA: Especificación, Reutilización y Exploración del Espacio de Diseño

Marcos¹

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This PhD. thesis addresses the design and implementation of signal processing applications using reconfigurable FPGA platforms. This kind of platform exhibits high logic capability, incorporates dedicated signal processing elements and provides a low cost solution, which makes it ideal for the development of signal processing applications, where intensive data processing is required in order to obtain high performance.However, the cost associated to the hardware development on these platforms is high. While the increase in logic capacity of FPGA devices allows the development of complete systems, high-performance constraints require the optimization of operators at very low level. In addition to time constraints imposed by these applications, Area constraints are also applied related to the particular device, which force to evaluate and verify a design among different implementation alternatives. The design and implementation cycle for these applications can be tedious and long, being therefore normal that new FPGA models with a greater capacity and higher speed appear before completing the system implementation. Thus, the original constraints which guided the design of the system become useless.Different methods can be used to improve the productivity when developing these applications, and consequently shorten their design cycle. This PhD. Thesis focuses on the reuse of hardware components previously designed and verified. Although conventional HDLs allow the reuse of components already defined, their specification can be improved in order to simplify the process of incorporating new design components. Thus, a first part of the PhD. Thesis will focus on the specification of designs based on predefined components. This specification improves and simplifies the process of adding components to a description, but it also seeks to improve the quality of the design specified with better configuration options and even offering to report on features of the description.Hardware reuse of a component for its integration into a system largely depends on the information it offers. In this sense the conventional HDLs only provide together with the component description, the input/output interface and a set of parameters for its configuration, while other information is usually provided by external documentation. In the second part of the Thesis we will propose a formal way of encapsulation which aims to incorporate with the component description information that can be useful for its integration into other designs. This information will include features of the own implementation, but it will also support component configuration, and even information on how to configure and connect the component to carry out a function.Finally, the fast Fourier transform (FFT) will be chosen as a well-known signal processing application. It will be used as case study to illustrate the possibilities of porposed v specification and encapsulation formalisms. The objective of the FFT design is not only to show practical examples of the proposed s...

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A multi-layered XML schema and design tool for reusing and integrating FPGA IP

Cited by 8 publications

References 4 publications

IP-XACT extensions for Reconfigurable Computing

IP-XACT extensions for Reconfigurable Computing

Improving Hardware Reuse through XML-based Interface Encapsulation

Implementación de Algoritmos de Procesado de Señal sobre FPGA: Especificación, Reutilización y Exploración del Espacio de Diseño

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