This paper presents the architecture and VHDL design of a Two Dimensional Discrete Cosine Transform (2D-DCT) with Quantization and zigzag arrangement. This architecture is used as the core and path in JPEG image compression hardware. The 2D-DCT calculation is made using the 2D-DCT Separability property, such that the whole architecture is divided into two 1D-DCT calculations by using a transpose buffer. Architecture for Quantization and zigzag process is also described in this paper. The quantization process is done using division operation. This design aimed to be implemented in Spartan-3E XC3S500 FPGA. The 2D-DCT architecture uses 1891 Slices, 51I/O pins, and 8 multipliers of one Xilinx Spartan-3E XC3S500E FPGA reaches an operating frequency of 101.35 MHz One input block with 8 x 8 elements of 8 bits each is processed in 6604 ns and pipeline latency is 140 clock cycles .

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Abstract: Conventional Microstrip Patch Antenna's (MPA) are in small in size, but their gain is quite low for most applications. Long distance communication requires high gain antennas. For conventional applications that require high gain mostly depends on parabolic antennas and arrays. Manufacturing parabolic antennas became complex at high frequencies because of its bent geometry. Microstrip Patch Antennas are low profile, low cost, they come with ease of fabrication and results in high beam scanwidth and high gain when they were used as an array configuration. In this paper, square and circular shaped Microstrip Patch Antennas are excited with inset feed are analyzed to determine which shape of antenna works well at the Ku (12-18GHz) range of frequency. Return loss, VSWR, gain, and directivity parameters are considered to analyze the above configurations. CST studio suite tool was used to simulate the configurations.

This paper presents a frame work for hardware acceleration for post video processing system implemented on FPGA. The deblocking filter algorithms ported on SOC having Altera NIOS-II soft core processor.SOC designed with the help of SOPC builder .Custom instructions are chosen by identifying the most frequently used tasks in the algorithm and the instruction set of NIOS-II processor has been extended. Deblocking filter new instruction added to the processor that are implemented in hardware and interfaced to the NIOS-II processor. New instruction added to the processor to boost the performance of the deblocking filter algorithm. Use of custom instructions the implemented tasks have been accelerated by 5.88%. The benefit of the speed is obtained at the cost of very small hardware resources.

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