This paper presents a frame work for hardware acceleration for post video processing system implemented on FPGA. The deblocking filter algorithms ported on SOC having Altera NIOS-II soft core processor.SOC designed with the help of SOPC builder .Custom instructions are chosen by identifying the most frequently used tasks in the algorithm and the instruction set of NIOS-II processor has been extended. Deblocking filter new instruction added to the processor that are implemented in hardware and interfaced to the NIOS-II processor. New instruction added to the processor to boost the performance of the deblocking filter algorithm. Use of custom instructions the implemented tasks have been accelerated by 5.88%. The benefit of the speed is obtained at the cost of very small hardware resources.

Now a days Jobs are Scheduled in a single processor or more than one processor, a real time job is scheduled or executed based on requirements, An Successful task in embedded system ought to have constrained asset necessities: Memory, execution time and power utilization, these necessity are not generally simple to fulfil in real-time embedded system with hard task deadlines. In this paper we explore the effective time utilization, without influencing the deadline requirements of typical hard real time task ,there are no limitation on the new results each task can be periodic or sporadic ,with relative deadline which can be less than ,equivalent to or greater than its period, it is too fast , best-effort ,effective real time scheduling algorithm for a wide variety of job parameters.

Reed Solomon (RS) codes are a sort of non-binary cyclic codes. This code is widely used in wireless and mobile communication units. RS encoder along with RS decoder using UHD architecture is designed in this paper. In this brief, a novel low complexity reformulated inverse-free burst-error correction algorithm is developed. Then based on the Proposed RiBC algorithm, a Unified VLSI architecture is designed. It will be shown that, it can achieve high-speed, throughput and improved error correcting capability than Hard Decision Decoding (HDD) design with less area. A design of (7, 3) Reed Solomon encoder and Decoder are implemented using Verilog hardware description language (HDL) code, simulated and synthesized by XILINX ISE simulator.

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