Organic thin-fi lm transistors (OTFTs) [ 1 ] are compatible with large area fabrication techniques, and they may yield new paradigms for manufacturing that would reduce device costs for large area circuits. [ 2 ] Pentacene-based OTFTs are well studied; yet they can be compromised with regard to critical device parameters: on/off ratios, carrier mobilities, sub-threshold performance, and threshold voltages. Surface treatments for the SiO 2 gate dielectric [2][3][4][5][6][7][8] can be effective; typically, however, improvement is realized in only one of these critical areas, often to the detriment of the others. [ 5 , 6 , 9-11 ] Here we show that systematic structural modifi cation of self-assembled monolayers of phosphonates (SAMPs) fabricated on SiO 2 gate dielectrics can yield pentacene-based devices in which all four critical parameters are enhanced simultaneously. We hypothesize that phosphonate structural motifs enable two-dimensional SAMP surface coverage to translate to a three-dimensional one through controlled lateral spacing between vertically oriented acene units, which can affect crystallization of vapor-deposited pentacene.Our approach to surface modifi cation of the SiO 2 gate dielectric on a Si device is based on a simple procedure in which a dilute solution of a phosphonic acid is drawn down across the face of the Si substrate. This process, nicknamed the T-BAG, [ 12 , 13 ] enables formation of high quality SAMPs on these substrates under mild conditions. In previous work we showed that a surface chemistry design approach to transistor function optimization based on T-BAGged SAMPs, progressing from simple enhancement of surface wetting to inducing more specifi c SAMP-pentacene interactions, enabled systematic improvement in OTFT behavior. [ 14 , 15 ] Our best-performing OTFT was based on a SAMP of 9-phosphonanthacene ( 1 ). Anthracenebased phosphonates are electronically acceptable for SiO 2 gate dielectric modifi cation: Their SAMP constituents should have a band gap larger than that of pentacene itself (1.86eV by optical absorption); [ 16 ] thus the SAMP would not create inherent trapping states. Furthermore, an anthracene-based SAMP and pentacene should have only C-H bond-π -system interactions, not stronger bonding ones that could, themselves, create trapping states in the semiconductor gap. Indeed, we found that OTFTs fabricated on 100 nm SiO 2 gate dielectrics terminated with a SAMP of 1 showed high on/off ratios, good threshold voltages, and subthreshold slopes as steep as 200 mV/decade [ 14 , 15 ] in contrast to devices prepared on untreated SiO 2 where subthreshold slopes on the order of about 5 V/decade, and threshold voltages of tens of volts are typical. [ 11 ] Pentacene-based devices fabricated with SAMPs of 1 were also compared to devices made with octadecyl trichlorosilane and with its SAMP analog, octadecylphosphonic acid. These three types of devices all had hole mobilities that were indistinguishable within experimental error. [ 14 , 15 ] Tight molecular packing of 1 on the ...

Inverted perovskite solar cells (p-i-n PSCs) have been fascinated due to rapid progress of performance in recent years. PEDOT: PSS is commonly used hole transport material (HTM) in p-i-n PSCs which is hygroscopic and acidic in nature that leads towards poor performance of device thus hinders commercialization of PSCs. Therefore, it is necessary to replace PEDOT: PSS with stable HTM in p-i-n PSCs. In this paper, theoretical study is carried out to investigate various physical parameters that can affect the performance of p-i-n PSCs with copper iodide (CuI) as HTM and phenyl-C61-butyric acid methyl ester (PCBM) as ETM. These parameters include the effect of doping density of ETM, absorber, and HTM as well as defect density and thickness of absorber on the performance of p-i-n PSCs. In addition, hole mobility and thickness of HTM is also investigated. It is found that performance of p-i-n PSC is strongly dependent on defect density and thickness of absorber layer while other physical parameters have minor influence on the performance of device. Upon final optimization, device attains PCE of more than 21 % which is encouraging. These results show that CuI as HTM is a potential choice for p-i-n PSCs.

Pentacene is a well-known conjugated organic molecule with high mobility and a sensitive photo response. It is widely used in electronic devices, such as in organic thin-film transistors (OTFTs), organic light-emitting diodes (OLEDs), photodetectors, and smart sensors. With the development of flexible and wearable electronics, the deposition of good-quality pentacene films in large-scale organic electronics at the industrial level has drawn more research attention. Several methods are used to deposit pentacene thin films. The thermal evaporation technique is the most frequently used method for depositing thin films, as it has low contamination rates and a well-controlled deposition rate. Solution-processable methods such as spin coating, dip coating, and inkjet printing have also been widely studied because they enable large-scale deposition and low-cost fabrication of devices. This review summarizes the deposition principles and control parameters of each deposition method for pentacene and its derivatives. Each method is discussed in terms of experimentation and theory. Based on film quality and device performance, the review also provides a comparison of each method to provide recommendations for specific device applications.

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