A brain tumor is a problem that threatens life and impedes the normal working of the human body. The brain tumor needs to be identified early for the proper diagnosis and effective treatment planning. Tumor segmentation from an MRI brain image is one of the most focused areas of the medical community, provided that MRI is non-invasive imaging. Brain tumor segmentation involves distinguishing abnormal brain tissue from normal brain tissue. This paper presents a systematic literature review of brain tumor segmentation strategies and the classification of abnormalities and normality in MRI images based on various deep learning techniques, interbreeding. It requires presentation and quantitative analysis, from standard segmentation and classification methods to the best class strategies.

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In the last decade many efficient VLSI architectures were designed to implement the discrete wavelet transform using the lifting scheme. Most of these architectures do not operate in real-time. This paper presents a scalable real time VLSI architectural to compute an integer wavelet transform (IWT) using the lifting scheme for (5/3) biorthogonal filter. The proposed architecture is projected on (XC3S700A FG484) FPGA chip embedded on a Spartan 3A starter kit board. An efficient formula is driven for controlling the delay introduced between tandem architectures that are adapted to work in real-time. The layout of the integrated VLSI structure is simple and can be connected easily in tandem for computing IWT in real time.A hard threshold module is designed and attached with proposed architecture to implement real time denosing application. The achievement of the proposed architecture along with supplement hard threshold module is assessed by denoising a four benchmarks signals corrupted by adding white Gaussian noise. The result outcomes show that the proposed IWT architecture has powerful performance in the real time wavelet based signal denoising process. The architecture data word length is selected as 11-bits to avoided arithmetic overflow for two's complement 8-bit integer data input. The maximum operating frequency of the proposed architecture varies from 26 MHz in 1-level to 14MHz in 5-level for decomposition/ reconstruction with hard threshold module in an FPGA implementation. The hardware utilization varies from (50%) in 1-level to (97%) for 5-level.

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