<p>The lightweight cryptography is used for low available resources devices such as radio frequency identification (RFID) tags, internet of things (IoTs) and wireless sensor networks. In such case, the lightweight cryptographic algorithms should consider power consumption, design area, speed, and throughput. This paper presents a new architecture of mCrypton lightweight cryptographic algorithm which considers the above-mentioned conditions. Resource-shared structure is used to reduce the area of the new architecture. The proposed architecture is implemented using ISE Xilinx V14,5 and Spartan 3 FPGA platform. The simulation results introduced that the proposed design area is 375 of slices, up to 302 MHz operating frequency, a throughput of 646 Mbps, efficiency of 1.7 Mbps/slice and 0.089 Watt power consumption. Thus, the proposed architecture outperforms similar architectures in terms of area, speed, efficiency and throughput.</p>

The objective of this research is to analyze the microwave power absorption properties of Unsaturated Polyester Resin (UPR) composite reinforced with micro size river-shell with an aim to figure out the new formed composites with the best microwave power absorption scenario. The composites were prepared by using river shell powder in micro-particle size as a filler material with unsaturated polyester composites. Using free-space transmission technique and within the x-band frequency range, the microwave power absorption properties were studied with varied percentages of river shell powder being loaded into the unsaturated polyester composites. River shells were introduced in an 50 microns particle size powder which was mixed in different weight percentages of 5, 10, and 15 % of a 12 cm square shape side length composite sample along with a thickness of 4 mm for each sample. The test specimens were prepared using the pre-mentioned weight amounts after mixing them with the Unsaturated Polyester Resin (UPR) compositions and in accordance with ASTM standard. Number of teste samples are four represented by pure, 5 %, 10 %, and 15 % of river-shell reinforced polyester composites. It has been found that the 5 % is the case when maximum power absorption presents higher levels than other loading percentages. Therefore, such kind of composites can be established under focus in those applications at which their trends is about necessity and importance of microwave power absorption.

In this paper, a fast design and implementation for sequential multiplier is presented. The suggested approach of implementation incorporates a definition of iterative addition that reduces the number of additions required in calculating the product of two binary numbers. The proposed implementation of sequential multiplier eliminates all shift operations required by conventional sequential multiplier to only one shift operation with the final accumulated result. Proposed and conventional designs of sequential multiplier are simulated in Quartus II synthesis software tool using Verilog implementation. According to the simulation results, the proposed implementation of sequential multiplier is better than conventional implementation in terms of delay time and power consumption. The proposed sequential multiplier shows an average improvement of 17.15% in delay time compared to conventional sequential multiplier.

Adders are the heart of data path circuits for any processor in digital computer and signal processing systems. Growth in technology keeps supporting efficient design of binary adders for high speed applications. In this paper, a fast and area-efficient modified carry save adder (CSA) is presented. A multiplexer based design of full adder is proposed to implement the structure of the CSA. The proposed design of full adder is employed in designing all stages of traditional CSA. By modifying the design of full adder in CSA, the complexity and area of the design can be reduced, resulting in reduced delay time. The VHDL implementations of CSA adders including (the proposed version, traditional CSA, and modified CSAs presented in literature) are simulated using Quartus II synthesis software tool with the altera FPGA EP2C5T144C6 device (Cyclone II). Simulation results of 64-bit adder designs demonstrate the average improvement of 17.75%, 1.60%, and 8.81% respectively for the worst case time, thermal power dissipation and number of FPGA logic elements.

Voice commands recognition is a way of understanding human speech and converting it to a communication input of computer. Based on the data used to feed the voice recognition system, systems could be classified as dependent or independent systems. In this paper, a dependent voice commands selective system is presented. The system uses the spectral subtraction algorithm for noise cancellation. A new algorithm is named Select Matching Command Algorithm SMCA is used for matching voice command identification. Six different users (3 male and 3 female) are used to test the system. Each user tests the system two times, one by using twenty four voice commands samples previously selected and other time by using another twenty four voice commands out of the twenty four preselected samples. The proposed system is able to correctly identify the matching voice commands 90.97% of the time when testing the system with the predefined voice commands. Testing the system with voice commands out of the predefined commands shows 92.36 % of no matching identification. According to the results noted from the six users, overall percent of selective accuracy of the suggested system is 91.67 %.