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With the development of new technologies, the operating frequencies on chip are increasing at a faster rate, such as computational methods, utilization of high-frequency clocks, digital circuits, etc. The process-technology-independent I/O standard, low-voltage differential signaling (LVDS), is basically developed for low-voltage, low-power, low-noise, and high-speed I/O interfaces. Low power is owing to the use of very small differential swing, while low noise is owing to essential nature of the differential circuits. Based upon ANSI TIA/EIA-644 LVDS standard, this paper presents a low-voltage and high-speed LVDS driver. A Common-mode feedback (CMFB) and a pull-up/down circuits were suggested as carried out by a standard 0.35-μm complementary metal oxide semiconductor (CMOS) process with a die area of 0.115 mm 2 . The measured results present that the driver works well at 1.5 Gbps, and the static current is less than 11.5 mA under 3.3 V. Keywords CMFB · High speed · LVDS · Rise/fall time IntroductionLVDS driver plays an important role in point-to-point communication with more and more data stream quantity and increasing data rate, as microprocessor main board, high-speed ADC/DAC, optical transmission links, etc [1].While the scaled CMOS technology continues to enhance the speed of operating speed but the I/O interface still confines the rate of data process, so the LVDS I/O interface becomes necessary. The point-to-point LVDS interface is shown in Fig. 110.1. Saving by a different scheme for transmission, termination, and a low-voltage swing, LVDS completes significant power [2]. LVDS standards put relatively stringent requirement on the tolerance influencing the output levels, gaining interesting design issues if low-cost solutions with neither external components nor trimming procedures are required. In the meantime, the very large tolerance for the common-mode

A capacitor memory erasing technique for pipeline ADC is introduced, which insert a clearing phase to the traditional working timing sequence of the MDAC to erasing the residual charges on the sampling capacitor. The measurement shows that the 14-bit pipeline ADC adopting the proposed technique can achieve a sampling rate of 250MSPS with SNR 69dB, SFDR 80dB, compared with the traditional ADC of sampling rate 100MSPS, SNR 60dB, SFDR 71dB, which proves the proposed technique can improve the performances of pipeline ADCS obviously.