Hierarchical Temporal Memory is a new machine learning algorithm intended to mimic the working principle of neocortex, part of the human brain, which is responsible for learning, classification, and making predictions. Although many works illustrate its effectiveness as a software algorithm, hardware design for HTM remains an open research problem. Hence, this work proposes an architecture for HTM Spatial Pooler and Temporal Memory with learning mechanism, which creates a single image for each class based on important and unimportant features of all images in the training set. In turn, the reduction in the number of templates within database reduces the memory requirements and increases the processing speed. Moreover, face recognition analysis indicates that for a large number of training images, the proposed design provides higher accuracy results (83.5%) compared to only Spatial Pooler design presented in the previous works.

High voltage insulator detection and monitoring via drone-based aerial images is a cost-effective alternative in extreme winter conditions and complex terrains. The authors examine different surface conditions of the outdoor electrical insulator that generally occur under winter condition using image processing techniques and state-of-the-art classification methods. Two different types of classification approaches are compared: one method is based on neural networks (e.g. CNN, InceptionV3, MobileNet, VGG16, and ResNet50) and the other method is based on traditional machine learning classifiers (e.g. Bayes Net, Decision Tree, Lazy, Rules, and Meta classifiers). They are evaluated to discriminate the images of insulator surface exposed to freezing, wet, and snowing conditions. The results indicate that traditional machine learning methods with proper selection of features can show high classification accuracy. The classification of the insulator surfaces will assist in determining the insulator conditions, and take preventive measures for its protection.

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Mapping neuro-inspired algorithms to sensor backplanes of on-chip hardware require shifting the signal processing from digital to the analog domain, demanding memory technologies beyond conventional CMOS binary storage units. Using memristors for building analog data storage is one of the promising approaches amongst emerging non-volatile memory technologies. Recently, a memristive multi-level memory (MLM) cell for storing discrete analog values has been developed in which memory system is implemented combining memristors in voltage divider configuration. In given example, the memory cell of 3 sub-cells with a memristor in each was programmed to store ternary bits which overall achieved 10 and 27 discrete voltage levels. However, for further use of proposed memory cell in analog signal processing circuits data encoder is required to generate control voltages for programming memristors to store discrete analog values. In this paper, we present the design and performance analysis of data encoder that generates write pattern signals for 10 level memristive memory.

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