Negative bias temperature instability (NBTI) has become one of the major causes for temporal reliability degradation of nanoscale circuits. Due to its complex dependence on operating conditions, it is a tremendous challenge to the existing timing analysis flow. In order to get the accurate aged delay of the circuit, previous research mainly focused on the gate level or lower. This paper proposes a low-runtime and high-accuracy machining learning framework on the circuit path level firstly, which can be formulated as a multi-input–multioutput problem and solved using a linear regression model. A large number of worst-case path candidates from ISCAS’85, ISCAS’89, and ITC’99 benchmarks were used for training and inference in the experiment. The results show that our proposed approach achieves significant runtime speed-up with minimal loss of accuracy.

With the aggressive scaling of feature size, Negative Bias Temperature Instability (NBTI) and Process Variation (PV) have become major issues for circuit reliability and yield. In this paper, we analyze the variation of gate delay by jointly considering NBTI and PV effects. Using Gaussian Process Regression (GPR) learning interface, a Statistical Gate Delay Extraction (SGDE) framework is proposed. Typical types of logic gates are simulated with commercial 28 nm technology for verifying the performance of SGDE in the experiment. Compared to the golden data, the results show that our proposed approach achieves minimal loss of accuracy with significant runtime speed-up.