The directed self-assembly (DSA) and pattern transfer of poly(5-vinyl-1,3-benzodioxole-block-pentamethyldisilylstyrene) (PVBD-b-PDSS) is reported. Lamellae-forming PVBD-b-PDSS can form well resolved 5 nm (half-pitch) features in thin films with high etch selectivity. Reactive ion etching was used to selectively remove the PVBD block, and fingerprint patterns were subsequently transferred into an underlying chromium hard mask and carbon layer. DSA of the block copolymer (BCP) features resulted from orienting PVBD-b-PDSS on guidelines patterned by nanoimprint lithography. A density multiplication factor of 4× was achieved through a hybrid chemo-/grapho-epitaxy process. Cross-sectional scanning tunneling electron microscopy/electron energy loss spectroscopy (STEM/EELS) was used to analyze the BCP profile in the DSA samples. Wetting layers of parallel orientation were observed to form unless the bottom and top surface were neutralized with a surface treatment and top coat, respectively.

Top-down patterning along with metal-assisted chemical etching (MACE) can enable the fabrication of highly controlled wafer-scale silicon nanowires (Si-NWs). Maximizing the NW aspect ratio, while avoiding collapse, can enable many important applications. A precise experimental technique has been developed here to study the onset of Si-NW collapse. This experimental approach has resulted in unexpectedly tall Si-NWs for oversized wires separated by sub-50-nm gaps. As compared to known theory, a factor of 4.5 increase in maximum aspect ratio was achieved for uncollapsed nanowires with 200-nm pitch and 25-nm spacing. This discrepancy between known theory and experimental results was eliminated when the gold-resist caps (which are a feature of our MACE process) on top of these nanowires were removed. This led us to incorporate electrostatic repulsion into known theoretical formulations, which matched the experimental results. In summary, this work provides new experimental and theoretical insights into nanowire collapse behavior.

The semiconductor industry’s transition to three-dimensional (3D) logic and memory devices has revealed the limitations of plasma etching in reliable creation of vertical high aspect ratio (HAR) nanostructures. Metal-assisted chemical etch (MacEtch) can create ultra-HAR, taper-free nanostructures in silicon, but the catalyst used for reliable MacEtchgoldis not CMOS (complementary metal–oxide–semiconductor)-compatible and therefore cannot be used in the semiconductor industry. Here, for the first time, we report a ruthenium MacEtch process that is comparable in quality to gold MacEtch. We introduce new process variablescatalyst plasma pretreatment and surface areato achieve this result. Ruthenium is particularly desirable as it is not only CMOS-compatible but has also been introduced in semiconductor fabrication as an interconnect material. The results presented here remove a significant barrier to adoption of MacEtch for scalable fabrication of 3D semiconductor devices, sensors, and biodevices that can benefit from production in CMOS foundries.

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