This brief proposes a fully dynamic discrete-time ADC using closed-loop two-stage cascoded floating inverter amplifiers (FIA). The proposed FIA uses a non-cascoded FIA as the 1 st stage and a cascoded one as the 2 nd . By using this arrangement as well as applying metal-insulator-metal (MIM) capacitors for floating reservoir capacitors, it stably achieves high gain even with the input common-mode voltage fluctuation without an additional CMFB nor calibrations. The proposed ADC fabricated in a 65 nm standard CMOS process realizes a fully dynamic operation without calibration and achieves 88.5 dB SNDR, 97.9 dB SFDR with an OSR of 256. It consumes 43.5 μW from a 1V supply at a 10 MHz sampling frequency.

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