Abstract. This research presents a Field Programmable Gate Array (FPGA) implementation of a taste recognition model. The model is based on simple integrate and fire neurons and facilitates an on-line learning. The whole system, including the hardware required to build (evolve) the network was hosted on one FPGA chip. The implementation used 45% of the logic elements, 76% of the memory, and 23% of the dedicated multiplier slices of the chip. FPGA size was sufficient for 64 neurons with up to 64 synapses each (a total of 4096 synapses). The proposed FPGA implementation was successfully applied to a classification problem of taste recognition and the FPGA implementation was at least 10 times faster when evolving the network and 74 times faster during the classification than the software simulations executed by a stand-alone PC.