A design strategy for the synthesis of high-selectivity/low-order analog filters in Complementary Metal-Oxide-Semiconductor (CMOS) technology for very high frequency (VHF) applications is presented. The methodology for the reconstitution of a given transfer function by means of Signal Flow Graphs (SFG) manipulation in canonical form is proposed leading to a fully differential g m -C biquad filter. As a practical example, the design of a notch filter intended to suppress interferers in the lower sideband (400 MHz) of the Medical Implant Communication Service (MICS), in single-poly, 6-metal layers; Mixed-Signal/RF 0.18 µm CMOS technology is realized. To compare the performance of the proposal with some other solution, the design of a 7th order elliptic notch filter based on Frequency Dependent Negative Resistors (FDNRs) was also accomplished. The attained simulation results prove that the proposal is competitive compared to the FDNR solution and some other state-of-the-art filters reported in the literature. The most salient features of the proposed notch biquad include: the selectivity, whose value is comparable to that of a 7th order elliptic approach and some other 3rd order filters; a high-frequency operation without resonators; linearity, with a +15 dBm I I P 3 ; a reduced form factor with a total occupied area of 0.004282 mm2 and mostly a low design complexity.

The design and characterization of a CMOS circuit for Morlet wavelet generation is introduced. With the proposed Morlet wavelet circuit, it is possible to reach a low power consumption, improve standard deviation (σ) control and also have a small form factor. A prototype in a double poly, three metal layers, 0.5µm CMOS process from MOSIS foundry was carried out in order to verify the functionality of the proposal. However, the design methodology can be extended to different CMOS processes. According to the performance exhibited by the circuit, may be useful in many different signal processing tasks such as nonlinear time-variant systems.

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JINST 15 C03043of charge generated within each individual SiPM on the one side, and the duration of each event on the other, as well as a Delta-Sigma (∆-Σ) analog-to-digital converter (ADC). An additional fieldprogrammable gate array (FPGA), the Xilinx Kintex 7, is used for signal processing and system controlling. We present the concept of the proposed DAQ system. K: Cherenkov detectors; Data acquisition circuits; Photon detectors for UV, visible and IR photons (vacuum) (photomultipliers, HPDs, others)