This paper describes the design, verification, implementation and fabrication of the Drac Vector IN-Order (DVINO) processor, a RISC-V vector processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The DVINO processor includes an internally developed two-lane vector processor unit as well as a Phase Locked Loop (PLL) and an Analog-to-Digital Converter (ADC). The paper summarizes the design from architectural as well as logic synthesis and physical design in CMOS 65nm technology.

This paper presents a 0.8-mW 0.2-mm 2 9-level second-order single-loop SC Delta-Sigma modulator (ΔΣM) ADC in 1.8-V 0.18-μm CMOS technology for low-power high-resolution sensing applications. The ΔΣM circuit features 94.6-dB peak SNDR in 50-kHz bandwidth and 103.5 dB SFDR up to -1 dB FS input for 2-Vpp differential full scale. The proposed built-in CDS flicker noise cancellation allows a net improvement of 10 dB FOM S . The bootstrapping-free CMOS circuits incorporate variable-mirror Class-AB switched OpAmps and a 10-μW resistor-less flash quantizer. The obtained 172.6-dB FOM S is competitive within the state-of-art high-resolution (SNDR > 90 dB) and generalpurpose (bandwidth > 20 kHz) SC ΔΣM ADCs.

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