Optical Networks-on-Chip (ONoCs) are a promising solution for high-performance multi-core integration with better latency and bandwidth than traditional Electrical NoCs. Wavelength-routed ONoCs (WRONoCs) offer yet additional performance guarantees. However, WRONoC design presents new EDA challenges which have not yet been fully addressed. So far, most topology analysis is abstract, i.e. overlooks layout concerns, while for layout the tools available perform Place and Route (P&R) but no topology optimization. Thus, a need arises for a novel optimization method combining both aspects of WRONoC design. In this paper such a method, PSION+, is laid out. This new procedure uses a linear programming model to optimize a WRONoC physical layout template to optimality. This templatebased optimization scheme is a new idea in this area that seeks to minimize problem complexity while keeping design flexibility. A simple layout template format is introduced and explored. Finally, multiple model reduction techniques to reduce solver run-time are also presented and tested. When compared to the state-ofthe-art design procedure, results show a decrease in maximum optical insertion loss of 41%.

No abstract

No abstract

Optical Networks-on-Chip (ONoCs) are becoming more and more appealing due to rising network requirements in integrated circuits. One important aspect in ONoC design is the amount of crosstalk generated by the network because crosstalk and Signal-to-Noise Ratio (SNR) are strong limiting factors to network scale and performance. Calculation of crosstalk is thus essential for effective ONoC design. Motivated by this fact, we developed a new general linear algebra based method to calculate the steady-state of any system obeying a simple set of rules. We prove that ONoCs follow these rules and show how this general method can be applied in the particular case of ONoCs to calculate accurate first-order and infinite-order crosstalk and SNR results for any ONoC network.

No abstract