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Performing inference of Convolutional Neural Networks (CNNs) on Internet of Things (IoT) edge devices ensures both privacy of input data and possible run time reductions when compared to a cloud solution. As most edge devices are memory- and compute-constrained, they cannot store and execute complex CNNs. Partitioning and distributing layer information across multiple edge devices to reduce the amount of computation and data on each device presents a solution to this problem. In this article, we propose DeeperThings, an approach that supports a full distribution of CNN inference tasks by partitioning fully-connected as well as both feature- and weight-intensive convolutional layers. Additionally, we jointly optimize memory, computation and communication demands. This is achieved using techniques to combine both feature and weight partitioning with a communication-aware layer fusion method, enabling holistic optimization across layers. For a given number of edge devices, the schemes are applied jointly using Integer Linear Programming (ILP) formulations to minimize data exchanged between devices, to optimize run times and to find the entire model’s minimal memory footprint. Experimental results from a real-world hardware setup running four different CNN models confirm that the scheme is able to evenly balance the memory footprint between devices. For six devices on 100 Mbit/s connections the integration of layer fusion additionally leads to a reduction of communication demands by up to 28.8%. This results in run time speed-up of the inference task by up to 1.52x compared to layer partitioning without fusing.

State-of-the-art microfluidic systems rely on relatively expensive and bulky off-chip infrastructures. The core of a system—the microfluidic chip—requires a clean room and dedicated skills to be fabricated. Thus, state-of-the-art microfluidic systems are barely accessible, especially for the do-it-yourself (DIY) community or enthusiasts. Recent emerging technology—3D-printing—has shown promise to fabricate microfluidic chips more simply, but the resulting chip is mainly hardened and single-layered and can hardly replace the state-of-the-art Polydimethylsiloxane (PDMS) chip. There exists no convenient fluidic control mechanism yet suitable for the hardened single-layered chip, and particularly, the hardened single-layered chip cannot replicate the pneumatic valve—an essential actuator for automatically controlled microfluidics. Instead, 3D-printable non-pneumatic or manually actuated valve designs are reported, but their application is limited. Here, we present a low-cost accessible all-in-one portable microfluidic system, which uses an easy-to-print single-layered 3D-printed microfluidic chip along with a novel active control mechanism for fluids to enable more applications. This active control mechanism is based on air or gas interception and can, e.g., block, direct, and transport fluid. As a demonstration, we show the system can automatically control the fluid in microfluidic chips, which we designed and printed with a consumer-grade 3D-printer. The system is comparably compact and can automatically perform user-programmed experiments. All operations can be done directly on the system with no additional host device required. This work could support the spread of low budget accessible microfluidic systems as portable, usable on-the-go devices and increase the application field of 3D-printed microfluidic devices.

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Embedded memories increasingly dominate SoC designs -whether chip area, performance, power consumption, manufacturing yield or design time are considered. ITRS data indicate that the embedded memory contents of ICs may increase from 20% in 1999 to 90% at the SOnm node by the end of the decade. Therefore, even more than today, the success of tomorrow's SoC design will depend on the availability of high-quality embedded memories. Advanced process technologies pose new challenges for meeting these quality criteria. Some of the challenges are: providing flexible redundancy solutions for embedded SRAMs; designing competitive memories despite ever increasing leakage currents; reducing SRAM susceptibility to soft-error rate (SER). These challenges are bringing about the need for significant innovations in design of embedded memories, much more so than in recent previous process generations. In the presentation, the challenges will be outlined and solutions will be proposed. The focus of the discussion will be on SRAM/ROM, but other technologies such as eDRAM and "IT SRAM" will also be addressed. About Ulf SchlichtmannAs Senior Director for Cells and Memories of Infineon Technologies AG, Ulf Schlichtmann is responsible for all design libraries, from definition through development to silicon verification, rampup and support. In this role, he is charged with ensuring that innovative high-quality design libraries enable product designers to easily utilize the features of today's advanced process technologies. Previously, he directed a major improvement project to increase development productivity through increased reuse. Before that, he held various technical and management positions related to design libraries, design automation and reuse programs.