Tomorrows high-quality SoCs require high-quality embedded memories today

Abstract

Embedded memories increasingly dominate SoC designs -whether chip area, performance, power consumption, manufacturing yield or design time are considered. ITRS data indicate that the embedded memory contents of ICs may increase from 20% in 1999 to 90% at the SOnm node by the end of the decade. Therefore, even more than today, the success of tomorrow's SoC design will depend on the availability of high-quality embedded memories. Advanced process technologies pose new challenges for meeting these quality criteria. Some of the challenges are: providing flexible redundancy solutions for embedded SRAMs; designing competitive memories despite ever increasing leakage currents; reducing SRAM susceptibility to soft-error rate (SER). These challenges are bringing about the need for significant innovations in design of embedded memories, much more so than in recent previous process generations. In the presentation, the challenges will be outlined and solutions will be proposed. The focus of the discussion will be on SRAM/ROM, but other technologies such as eDRAM and "IT SRAM" will also be addressed. About Ulf SchlichtmannAs Senior Director for Cells and Memories of Infineon Technologies AG, Ulf Schlichtmann is responsible for all design libraries, from definition through development to silicon verification, rampup and support. In this role, he is charged with ensuring that innovative high-quality design libraries enable product designers to easily utilize the features of today's advanced process technologies. Previously, he directed a major improvement project to increase development productivity through increased reuse. Before that, he held various technical and management positions related to design libraries, design automation and reuse programs.

Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding

“…As the areas of SoCs and microprocessors are increasingly dominated by the embedded memory system, overall chip yield will closely track the on-die memory yield [39]. As discussed in Section 2.3, scaling conventional horizontal per-word ECC to cover multi-bit errors incurs considerable overheads, and thus memories can only practically employ an error detecting code or SECDED ECC.…”

“…Nanoscale components themselves are increasingly likely to fail, and the growing amount of on-chip memory creates more possible points of failure. As designers integrate more of the memory hierarchy onto the processing die, the number and size of memory arrays on these system-ona-chip (SoC) and microprocessors will increase [39]. Therefore, errors occurring in the embedded memory systems are a growing threat to the overall SoC and processor reliability and yield.…”

Efficient Use of Unused Spare Columns for Reducing Memory Miscorrections

“…Nano-scale components themselves are increasingly likely to fail, and the growing amount of on-chip memory creates more possible points of failure. As designers integrate more of the memory hierarchy onto the processing die, the number and size of memory arrays on these system-onchip (SoC) and microprocessors will increase [1]. Therefore, errors occurring in the embedded memory systems are a growing threat to the overall SoC and processor reliability and yield.…”

Efficient Use of Unused Spare Columns to Improve Memory Error Correcting Rate

“…Nano-scale components themselves are increasingly likely to fail, and the growing amount of on-chip memory creates more possible points of failure. As designers integrate more of the memory hierarchy onto the processing die, the number and size of memory arrays on these systemon-chip (SoC) and microprocessors will increase [1]. Therefore, errors occurring in the embedded memory systems are a growing threat to the overall SoC and processor reliability and yield.…”