No abstract

The majority of the existing experimental, theoretical and modeling works on electromigration (EM) are focused on simple, via-to-via structures, but complex interconnect structures have not been studied well. The lack of correct models for such interconnects may result in either conservative or weak design decisions which may result in catastrophic reliability failures. This paper proposes a physical model which holds for material migration as well as for lattice vacancy generation/annihilation. Using the developed model, well known circuit level EM assessment methods are examined by finite element modeling and simulation. The paper provides a compact model for EM analysis which can be easily implemented in CAD tools. We also explain some recent experimental results and empirical models published by other researchers.

We investigate the effect of electrically induced thermal load on interconnect reliability and aging. We propose new models for uniform and non-uniform temperature evolution and its steady state distribution in interconnects considering Joule heating and heat convection. The models are verified by comparing the results against those of finite element experiments. We apply our models to study material migration induced aging and failures. We discuss how different non-uniform temperature profiles affect interconnect lifetime. We propose new formulas for accurate temperature aware assessment of the mortality of interconnects. We demonstrate that neglecting thermal effects in modern technologies may lead to incorrect conclusions about interconnect mortality. We also provide a method for modeling the true mean time to failure based on underlying physics.

No abstract

This paper is concerned with reliability evaluation for logic networks. The proposed approach is based on the notation of probabilistic transfer matrices (PTM), which is extended from binary to multivalued gates and circuits. The presented approach models all sources of uncertainty in the multivalued circuits, including faulty gates, noisy signals and unreliable interconnections, in order to derive the overall reliability of a given multivalued circuit.