CdTe devices have reached efficiencies of 22% due to continuing improvements in bulk material properties, including minority carrier lifetime. Device modeling has helped to guide these device improvements by quantifying the impacts of material properties and different device designs on device performance. One of the barriers to truly predictive device modeling is the interdependence of these material properties. For example, interfaces become more critical as bulk properties, particularly, hole density and carrier lifetime, increase. We present device-modeling analyses that describe the effects of recombination at the interfaces and grain boundaries as lifetime and doping of the CdTe layer change. The doping and lifetime should be priorities for maximizing open-circuit voltage (Voc) and efficiency improvements. However, interface and grain boundary recombination become bottlenecks for device performance at increased lifetime and doping levels. This work quantifies and discusses these emerging challenges for next-generation CdTe device efficiency.

This work analyzes heterojunction with intrinsic thin layer (HIT) solar cells using numerical simulations. The differences between the device physics of cells with p- and n-type crystalline silicon (c-Si) wafers are substantial. HIT solar cells with n-type wafers essentially form a n/p/n structure, where tunneling across the junction heterointerfaces is a critical transport mechanism required to attain performance exceeding 20%. For HIT cells with p-type wafers, only tunneling at the back-contact barrier may be important. For p-wafer cells, the hydrogenated amorphous silicon (a-Si:H) between the indium tin oxide (ITO) and crystalline silicon may act as a passivating buffer layer but, otherwise, does not significantly contribute to device performance. For n-wafer cells, the carrier concentration and band alignment of this a-Si:H layer are critical to device performance.

World-record power conversion efficiencies for Cu(In,Ga)Se2 (CIGS) solar cells have been achieved via a post-deposition treatment with alkaline metals, which increases the open-circuit voltage and fill factor. We explore the role of the potassium fluoride (KF) post-deposition treatment in CIGS by employing energy- and time-resolved photoluminescence spectroscopy and electrical characterization combined with numerical modeling. The bulk carrier lifetime is found to increase with post-deposition treatment from 255 ns to 388 ns, which is the longest charge carrier lifetime reported for CIGS, and within ∼40% of the radiative limit. We find evidence that the post-deposition treatment causes a decrease in the electronic potential fluctuations. These potential fluctuations have previously been shown to reduce the open-circuit voltage and the device efficiency in CIGS. Additionally, numerical simulations based on the measured carrier lifetimes and mobilities show a diffusion length of ∼10 μm, which is ∼4 times larger than the film thickness. Thus, carrier collection in the bulk is not a limiting factor for device efficiency. By considering differences in doping, bandgap, and potential fluctuations, we present a possible explanation for the voltage difference between KF-treated and untreated samples.

The performance of CdTe solar cells can be very sensitive to the emitter/absorber interface, especially for high-efficiency cells with high bulk lifetime. Performance losses from acceptor-type interface defects can be significant when interface defect states are located near mid-gap energies. Numerical simulations show that the emitter/absorber band alignment, the emitter doping and thickness, and the defect properties of the interface (i.e., defect density, defect type, and defect energy) can all play significant roles in the interface recombination. In particular, a type I heterojunction with small conduction-band offset (0.1 eV ≤ ΔEC ≤ 0.3 eV) can help maintain good cell efficiency in spite of high interface defect density, much like with Cu(In,Ga)Se2 (CIGS) cells. The basic principle is that positive ΔEC, often referred to as a “spike,” creates an absorber inversion and hence a large hole barrier adjacent to the interface. As a result, the electron-hole recombination is suppressed due to an insufficient hole supply at the interface. A large spike (ΔEC ≥ 0.4 eV), however, can impede electron transport and lead to a reduction of photocurrent and fill-factor. In contrast to the spike, a “cliff” (ΔEC < 0 eV) allows high hole concentration in the vicinity of the interface, which will assist interface recombination and result in a reduced open-circuit voltage. Another way to mitigate performance losses due to interface defects is to use a thin and highly doped emitter, which can invert the absorber and form a large hole barrier at the interface. CdS is the most common emitter material used in CdTe solar cells, but the CdS/CdTe interface is in the cliff category and is not favorable from the band-offset perspective. The ΔEC of other n-type emitter choices, such as (Mg,Zn)O, Cd(S,O), or (Cd,Mg)Te, can be tuned by varying the elemental ratio for an optimal positive value of ΔEC. These materials are predicted to yield higher voltages and would therefore be better candidates for the CdTe-cell emitter.