Recently, many efforts have been made to develop more efficient Inter-Vehicle Communication (IVC) protocols for ondemand route planning according to observed traffic congestion or incidents, as well as for safety applications. Because practical experiments are often not feasible, simulation of network protocol behavior in Vehicular Ad Hoc Network (VANET) scenarios is strongly demanded for evaluating the applicability of developed network protocols. In this work, we discuss the need for bidirectional coupling of network simulation and road traffic microsimulation for evaluating IVC protocols. As the selection of a mobility model influences the outcome of simulations to a great extent, the use of a representative model is necessary for producing meaningful evaluation results. Based on these observations, we developed the hybrid simulation framework Veins (Vehicles in Network Simulation), composed of the network simulator OMNeT++ and the road traffic simulator SUMO. In a proof-of-concept study, we demonstrate its advantages and the need for bidirectionally coupled simulation based on the evaluation of two protocols for incident warning over VANETs. With our developed methodology, we can advance the state-of-the-art in performance evaluation of IVC and provide means to evaluate developed protocols more accurately.

The rapid cycling synchrotron (RCS) radio frequency accelerating systems have been prepared for the beam commissioning scheduled in the middle of September 2007. Installations of cavities, power supplies and amplifiers were carried out. And, the systems have been checked for the combined operations. For the main synchrotron (50GeV-MR) accelerating systems, the high power examinations and final adjustments are ongoing. And, installations are planned in September 2007. Here, we report on various issues that had been found and solved during the examination and installation period.

No abstract

&straQ -A Distributed Globally ReplaceableRedundancy (DGR) scheme has been developed, which realizes a higher optimization of trade-off between yield and chip size. A newly developed yield simulator has demonstrated the effectiveness of the DGR scheme.

No abstract