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This paper presents a new multi-voltage SOI-BiCDMOS, which particularly focuses on "Power MOSFETs and BJTs rich automotive applications". This technology can integrate Nch LDMOSs and Pch LDMOSs which have 35V/6OV/8OV breakdown voltages, high packing density deep trench isolated BJTs, and a low cost 0 . 8~ CMOS, on a single chip. The six types of LDMOSs can be simultaneously fabricated with only two additional masks to a CMOS process, and these LDMOSs satisfy both low specific on-resistance and good SOA. Furthermore, in this technology a bonded SO1 wafer with 200mm diameter has been newly adopted in order to reduce chip cost.

We have developed a fab-wide APC system to control critical dimension (CD) of gate electrode length. We have also developed a model equation to predict gate CD by considering the structures of gate electrode and STI. This prediction model was also used to do factor analysis of gate CD variation. Effectiveness of the prediction model for feedforward control was evaluated by both simulation and experiment.

3 -1 M or i ii o s a t o Wa kaiiii y a, At s u g i-s li i , I< an ag aw a 2 4 3 -0 1, J a p a n Abstract A bipolar standard cell LSI design methodology for Gbit/s LSIs is described. A unique configuration of cell libraries which have internal fixed routing channels especially for differentjal clocks and a clock distribution scheme t h a t considers tlie equal length and load of differeiitial clocks makes it possible t o achieve a 1.8 Gbit/s 2.5 K-gate LSI.