A design methodology of bipolar standard cell LSIs for Gbit/s signal processing

Abstract

3 -1 M or i ii o s a t o Wa kaiiii y a, At s u g i-s li i , I< an ag aw a 2 4 3 -0 1, J a p a n Abstract A bipolar standard cell LSI design methodology for Gbit/s LSIs is described. A unique configuration of cell libraries which have internal fixed routing channels especially for differentjal clocks and a clock distribution scheme t h a t considers tlie equal length and load of differeiitial clocks makes it possible t o achieve a 1.8 Gbit/s 2.5 K-gate LSI.

A global router optimizing timing and area for high-speed bipolar LSI's

“…We tested three bipolar circuits. The rst circuit, C1, was the regenerator-section overhead processing circuit for a 10-Gbit/s transmission system [1]. The others were also for the transmission system.…”

“…The clock speeds of digital LSI's are rapidly increasing and some bipolar LSI's are reportedly able to process overGbit/s signals [1]. Therefore, the timing constraints for those LSI's are becoming much more crucial.…”

Post-layout optimization of power and timing for ECL LSIs

“…Advanced ECL LSIs can operate at a frequency of up to a few GHz [5,11]. ECL is the most promising and practical technology to construct high-speed measurement systems, B-ISDN systems such as SDH 1 signal processing, and so on.…”