Gate CD Control Considering Variation of Gate and STI Structure

Kurihara,; Tanaka, M.; Izawa,; Kawai,; Fujiwara,

doi:10.1109/issm.2006.4493032

Cited by 5 publications

(4 citation statements)

References 1 publication

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“…The variations in the STI step height and poly-Si thickness were found to cause 14 and 21% of the gate CD variation, respectively, although lithography and etching variations caused 47 and 11% of the gate variation, respectively. 113,114) To organize these variations over multiple processes, an advanced process control (APC) system is significant for improving the production yield. In this system, based on the gate length prediction model, precise variations in the gate length and STI structure are considered in the model equation.…”

Section: Control and Ler Reductionmentioning

confidence: 99%

Developments of Plasma Etching Technology for Fabricating Semiconductor Devices

Abe¹,

Yoneda

Fujiwara

2008

jjap

285

163

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Plasma etching technologies such as reactive ion etching (RIE), isotropic etching, and ashing/plasma cleaning are the currently used booster technologies for manufacturing all silicon devices based on the scaling law. The needs-driven conversion from the wet etching process to the plasma/dry etching process is reviewed. The progress made in plasma etching technologies is described from the viewpoint of requirements for the manufacturing of devices. The critical applications of RIE, isotropic etching, and plasma ashing/cleaning to form precisely controlled profiles of high-aspect-ratio contacts (HARC), gate stacks, and shallow trench isolation (STI) in the front end of line (FEOL), and also to form precise via holes and trenches used in reliable Cu/low-k (low-dielectric-constant material) interconnects in the back end of line (BEOL) are described in detail. Some critical issues inherent to RIE processing, such as the RIE-lag effect, the notch phenomenon, and plasma-induced damage including charge-up damage are described. The basic reaction mechanisms of RIE and isotropic etching are discussed. Also, a procedure for designing the etching process, which is strongly dependent on the plasma reactor configuration, is proposed. For the more precise critical dimension (CD) control of the gate pattern for leading-edge devices, the advanced process control (APC) system is shown to be effective.

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Section: Control and Ler Reductionmentioning

confidence: 99%

Developments of Plasma Etching Technology for Fabricating Semiconductor Devices

Abe¹,

Yoneda

Fujiwara

2008

jjap

285

163

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“…The TiN films evaluated include a crystalline PVD TiN film and several PEALD TiN films with varying crystallinity. Incoming resist mask thickness was thin at 14 nm, so the resist mask budget was increased before etching with an in situ mask reconstruction process (MRP) 11 developed by Hitachi, Ltd., outlined in Figure 1. The mask pattern was transferred to SiARC, amorphous-Carbon (a-C), SiO 2 and TiN to form a TiN hardmask on top of the p-SiOCH layer.…”

Section: Experimental Procedures 21 Pattern Evaluationmentioning

confidence: 99%

Evaluation of TiN hardmask films to prevent line wiggling due to plasma-induced film stress

Turnquist

Kofuji

Strzalka

et al. 2023

Advanced Etch Technology and Process Integration for Nanopatterning XII

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The impact of both intrinsic and plasma-induced stress of a TiN hardmask on line wiggling was investigated via etching of p-SiOCH with 28 nm pitch, line and space (L/S) EUV resist patterning. Experimental stacks included crystalline PVD TiN with an intrinsic stress of +0.1 GPa and several PEALD TiN films with varying crystallinity and intrinsic stresses ranging from -3.6 GPa (compressive) to +0.2 GPa (tensile). Results confirmed that reduction of intrinsic TiN stress can prevent wiggling1 when the mask is not exposed to plasma during process flow. However, when TiN is exposed to plasma as in a typical back end of line (BEOL) process2-3, compressive stress increased in all films and resulted in wiggling even in the patterned PVD TiN sample with low intrinsic stress. This global increase in compressive stress due to plasma exposure did not correlate with intrinsic stress values, therefore, this work suggests a greater focus should be placed on plasma-induced stress to avoid line wiggling when selecting a TiN film. Further investigation found that increased surface roughness of the TiN mask can decrease the risk of wiggling, and that surface roughness is influenced by p-SiOCH etch selectivity, indicating mask surface roughness should also be considered when evaluating line wiggling in BEOL, p-SiOCH etching.

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“…In addition, the interaction among the across-wafer trench depth, the gap-filled oxide deposition, and CMP polish rate distribution requires the optimization of all related processes to minimize the across-wafer step height variation. This is highly critical for improving the gate CD uniformity [4,5] and the gate profile. More details on such correlation are discussed in the next section.…”

Section: Sti Etchmentioning

confidence: 99%

A Study of 65nm Silicon Etch

et al. 2010

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The control of shallow trench isolation (STI) depth uniformity and poly gate profile necessitates the combination of more advanced silicon etch methodologies, in-situ measurements, and various relevant integration schemes. This paper presents a study of the difficulties and corresponding solutions in 65nm silicon etch with respect to process development and mass production. In the development phase, the STI trench profile and the depth uniformity of the STI depth can be well controlled by etch recipe tuning. In the mass production phase, we need to extend additional focus on the impact from different products on the inter-field variation of STI depth. Results show a good correlation of the depth to the pattern density variation. Such relationship has been utilized in feed-forward mode to deliver a robust process control. In addition, we also address the influence of oxide variation in STI fabrication and STI step height difference on the corresponding poly gate profile and the pits defects.

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Gate CD Control Considering Variation of Gate and STI Structure

Cited by 5 publications

References 1 publication

Developments of Plasma Etching Technology for Fabricating Semiconductor Devices

Developments of Plasma Etching Technology for Fabricating Semiconductor Devices

Evaluation of TiN hardmask films to prevent line wiggling due to plasma-induced film stress

A Study of 65nm Silicon Etch

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