The concept of Random Access Scan (RAS) where every Flip-Flop is addressed uniquely has been subject to criticism at the very thought. It seems at the first impulse that the cost associated with routing is overwhelming. This argument has shelved the idea for 25 years now. In this paper we propose an architecture that minimizes the signals to the RAS Flip-Flop (FF) and give an estimate of the increase in area due to the increase in gates and increase in routing. Two global signals, scanin and mode control, have been eliminated from the previous RAS designs presented in the literature. For n flip-flops, instead of routing n address wires, one to each FF, we use √ n wires in an xy matrix layout. A unique toggle mechanism is incorporated in the RAS FF that totally eliminates the scanin signal wire and reduces the vector set up to 60% compared to traditional serial scan (SS). The SS induces unnecessary circuit activity during scan and the circuit under test (CUT) dissipates an enormous amount of power. Our design reduces the power dissipation by 99%. The problem of delay testing is highly constrained in SS and the scan-cell is often modified to assist delay testing. Any single input change delay test can be directly applied in our design. Hence all testable paths in the circuit can be effectly tested without constraints. We also propose a multistage scanout system to observe the addressed FF avoiding a slow output bus with very high capacitance.