A random access scan architecture to reduce hardware overhead

Mudlapur, Anand; Agrawal, Vishwani D.; Singh, A.D.

doi:10.1109/test.2005.1583993

Cited by 25 publications

(19 citation statements)

References 33 publications

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“…Among the different RAS-based architectures that have been proposed to date, the Progressive Random Access Scan (PRAS) scheme proposed by Baik and Saluja [23] has the lowest hardware overhead, since it requires only two transistors per system flip flop; as a comparison, the scheme proposed by [21] requires 16 transistors per system flip flop.…”

Section: Progressive Random Access Scanmentioning

confidence: 99%

“…In the same year, Sheth and Savir proposed [18] a design for a scan latch that was utilized in [19] to design a latch-based RAS architecture with low hardware overhead. In 2005, Mudlapur, Agrawal and Singh, proposed in [20] a random access scan flip flop, which they subsequently utilized to propose, in [21], a Random Access Scan architecture with reduced overhead. Another research team, comprising Baik and Saluja, started working in the field in 2004 and proposed Random Access Scan as a solution to the problem of test power, test data volume and test time in [22].…”

Section: Introductionmentioning

confidence: 99%

“…This structure is favored in terms of routing overhead, since the column and row wires can be routed over different metal layers. Therefore, the total wire area is decreased [21]. …”

Section: Introductionmentioning

confidence: 99%

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Output response compaction in RAS-based schemes

Voyiatzis

Antonopoulou

Efstathiou

2009

2009 4th International Conference on Design &Amp; Technology of Integrated Systems in Nanoscal Era

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Scan design has been the backbone of design for testability schemes in industry because it provides for controllability and observability of the internal flip flops of the circuit. However, the serial scan causes high switching activity during testing which results in high power dissipation. Another problem that may appear in scan designs is unknown values, which can invalidate the final signature captured in the response verifier. An alternate to serial scan architecture is Random Access Scan (RAS). In RAS, flip-flops operate as addressable memory elements during test mode in a fashion similar to Random Access Memory (RAM). This approach reduces the time needed to set and observe the states of the flip-flops while at the same time the power dissipation is reduced by as much as 99% comparatively to serial scan.In this work we propose a response compaction scheme for RASbased architectures that results in lower hardware overhead compared to the response compaction scheme utilized in previous RAS-based schemes, while at the same time eliminates the problem of unknown values.

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Section: Progressive Random Access Scanmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Output response compaction in RAS-based schemes

Voyiatzis

Antonopoulou

Efstathiou

2009

2009 4th International Conference on Design &Amp; Technology of Integrated Systems in Nanoscal Era

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“…A toggle RAS in [9,10] and a Localized Random Access Scan (LRAS) method in [11] were proposed to reduce the routing complexity. Grouping for launch-oncapture delay testing can also reduce the power consumption [12].…”

Section: Introductionmentioning

confidence: 99%

A novel power-efficient IC test scheme

Deng

Chen

Guo

2017

IEICE Electron. Express

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A novel power-efficient IC test scheme is proposed, containing parallel test application (PTA) architecture and its procedure. PTA parallelizes the stimuli assignments and the vectors can be observed immediately once applied, which assures the shift safety timely and hence only logic test is required. The procedure contains two phases for each pattern. In shift phase, each clock chain is activated in turn and the vectors are assigned in parallel. In capture phase, all chains are captured simultaneously. Experimental results demonstrate that, compared with the traditional serial scan scheme, the proposal reduces average power by 88.48% and peak power by 53.36%.

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“…It arranges the flip-flops of a circuit in an array providing unique access to read and write single bits. In [9,10] a toggle flip-flop is used to invert a bit instead of writing it. While still incorporating a high area overhead, the results show that significant savings in test time and volume are possible if the next test pattern is setup by selectively updating the captured circuit response.…”

Section: Introductionmentioning

confidence: 99%

Bit-Flipping Scan - A unified architecture for fault tolerance and offline test

Imhof¹,

Wunderlich²

2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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Test is an essential task since the early days of digital circuits. Every produced chip undergoes at least a production test supported by on-chip test infrastructure to reduce test cost. Throughout the technology evolution fault tolerance gained importance and is now necessary in many applications to mitigate soft errors threatening consistent operation. While a variety of effective solutions exists to tackle both areas, test and fault tolerance are often implemented orthogonally, and hence do not exploit the potential synergies of a combined solution. The unified architecture presented here facilitates fault tolerance and test by combining a checksum of the sequential state with the ability to flip arbitrary bits. Experimental results confirm a reduced area overhead compared to a orthogonal combination of classical test and fault tolerance schemes. In combination with heuristically generated test sequences the test application time and test data volume are reduced significantly. Preprint General Copyright NoticeThis article may be used for research, teaching and private study purposes. Any substantial or systematic reproduction, re-distribution, re-selling, loan or sub-licensing, systematic supply or distribution in any form to anyone is expressly forbidden. This is the author's "personal copy" of the final, accepted version of the paper published by IEEE. Abstract-Test is an essential task since the early days of digital circuits. Every produced chip undergoes at least a production test supported by on-chip test infrastructure to reduce test cost. Throughout the technology evolution fault tolerance gained importance and is now necessary in many applications to mitigate soft errors threatening consistent operation. While a variety of effective solutions exists to tackle both areas, test and fault tolerance are often implemented orthogonally, and hence do not exploit the potential synergies of a combined solution.The unified architecture presented here facilitates fault tolerance and test by combining a checksum of the sequential state with the ability to flip arbitrary bits. Experimental results confirm a reduced area overhead compared to a orthogonal combination of classical test and fault tolerance schemes. In combination with heuristically generated test sequences the test application time and test data volume are reduced significantly.

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A random access scan architecture to reduce hardware overhead

Cited by 25 publications

References 33 publications

Output response compaction in RAS-based schemes

Output response compaction in RAS-based schemes

A novel power-efficient IC test scheme

Bit-Flipping Scan - A unified architecture for fault tolerance and offline test

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